Inventor

Christophe Figuet

Inventor
Crolles, FR

Overview

21→
Patents
2005–2019
Patent span
Electricity
Primary field (CPC H)

Patents· 21 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%
H10DInorganic electric semiconductor devices17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
H01LSemiconductor devices11%
C30BSingle-crystal growth7%
H10HInorganic light-emitting semiconductor devices having potential barriers6%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form3%
B82YSpecific uses or applications of nanostructures1%
F21KNon-electric light sources using luminescence1%
F21VFunctional features or details of lighting devices or systems thereof1%
PatentTitleYear
10,250,282Structure for radiofrequency applications201910,093,086Method for separating at least two substrates along a selected interface20189,716,029'Method for transferring a layer of a semiconductor and substrate comprising a confinement structure'20179,646,825'Method for fabricating a composite structure to be separated by exfoliation'20179,437,473'Method for separating at least two substrates along a selected interface'20169,276,070'Semiconductor structures including stacks of indium gallium nitride layers'20169,198,294'Electronic device for radiofrequency or power applications and process for manufacturing such a device'20158,975,165'III-V semiconductor structures with diminished pit defects and methods for forming the same'20158,742,428'Deposition methods for the formation of III/V semiconductor materials, and related structures'20148,575,010'Method for fabricating a semiconductor substrate'20138,329,571'Deposition methods for the formation of III/V semiconductor materials, and related structures'20128,309,437'(110) oriented silicon substrate and a bonded pair of substrates comprising said (110) oriented silicon substrate'20128,148,252'Methods of forming III/V semiconductor materials, and semiconductor structures formed using such methods'20128,084,784'Semiconductor heterostructure and method for forming same'20117,825,401'Strained layers within semiconductor buffer structures'20107,772,127'Semiconductor heterostructure and method for forming same'20107,608,526'Strained layers within semiconductor buffer structures'20097,544,976'Semiconductor heterostructure'20097,459,374'Method of manufacturing a semiconductor heterostructure'20087,387,953'Laminated layer structure and method for forming the same'20086,959,863'Method for selectively transferring at least an element from an initial support onto a final support'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005Based in Fontaine, FR· patent location history
2008–2019Patents assigned to SOITEC SILICON ON INSULATOR (20)· patent assignee history
2008–2019Based in Crolles, FR· patent location history
2009–2010Patents assigned to ASM INC (2)· patent assignee history
2011–2017Patents assigned to FIGUET CHRISTOPHE (10)· patent assignee history
2012–2015Patents assigned to TOMASINI PIERRE (4)· patent assignee history
2012–2015Patents assigned to KONONCHUK OLEG (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SOITEC SILICON ON INSULATOR202008–2019
FIGUET CHRISTOPHEself102011–2017
TOMASINI PIERRE42012–2015
ASM INC22009–2010
KONONCHUK OLEG22012–2015
Locations
LocationPatentsSpan
Crolles, FR202008–2019
Fontaine, FR12005