Inventor
ZHENGANG CHEN
Inventor
US
Overview
Patents· 48 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing45%
G11CStatic stores38%
H03MCoding11%
H04LTransmission of digital information, e.g. telegraphic communication5%
G01RMeasuring electric variables1%
PatentTitleYear
12,585,388Selectively enabling valley track for reading data202612,547,344Corrective read of a memory device with reduced latency202612,541,398Management of unmapped allocation units of a memory sub-system202612,511,059Power efficient codeword scrambling in a non-volatile memory device202512,505,899Power loss error detection using partial block handling202512,505,888Memory device producing metadata characterizing applied read voltage level with respect to voltage distributions202512,493,415Program pulse modification202512,431,202Memory read calibration based on memory device-originated metrics characterizing voltage distributions202512,386,515Modification of program voltage level with read or program-verify adjustment for improving reliability in memory devices202512,332,743Efficient memory use to support soft information in bit flipping decoders202512,301,254Early stopping of bit-flip low density parity check decoding based on syndrome weight202512,197,743Parity protection in non-volatile memory202512,086,058Self-seeded randomizer for data randomization in flash memory202412,067,264Power efficient codeword scrambling in a non-volatile memory device202412,007,837Redundancy metadata schemes for rain protection of large codewords202411,914,510Layer interleaving in multi-layered memory202411,907,580Corrective read of a memory device with reduced latency202411,870,461Failure-tolerant error correction layout for memory sub-systems202411,782,787Dynamic error control configuration for memory systems202311,775,381Redundancy metadata schemes for RAIN protection of large codewords202311,768,766Metadata aware copyback for memory devices202311,750,218Iterative error correction with adjustable parameters after a threshold number of iterations202311,726,671Memory access mode selection202311,709,771Self-seeded randomizer for data randomization in flash memory202311,688,485Self-adaptive read voltage adjustment using boundary error statistics for memories with time-varying error rates202311,688,467Defect detection in memories with time-varying bit error rate202311,632,132Configuring iterative error correction parameters using criteria from previous iterations202311,625,299Inserting temperature information into a codeword202311,615,830Performing a refresh operation based on a characteristic of a memory sub-system202311,579,809Performing a refresh operation based on a write to read time difference202311,561,734Selecting read voltage using write transaction data202311,545,230Manufacturer self-test for solid-state drives202311,526,395Write buffer management202211,520,491Parity protection in non-volatile memory202211,455,194Management of unmapped allocation units of a memory sub-system202211,438,012Failure-tolerant error correction layout for memory sub-systems202211,430,529Capacitance coupling parameter estimation in flash memories202211,410,743Self-adaptive read voltage adjustment using directional error statistics for memories with time-varying error rates202211,404,141Preemptive read refresh in memories with time-varying error rates202211,394,403Error correction based on rate adaptive low density parity check (LDPC) codes with flexible column weights in the parity check matrices202211,374,592Iterative error correction with adjustable parameters after a threshold number of iterations202211,341,046Layer interleaving in multi-layered memory202211,327,884Self-seeded randomizer for data randomization in flash memory202211,281,533Hybrid iterative error correcting and redundancy decoding operations for memory sub-systems202211,256,429Adjustment of a pre-read operation based on an operating temperature202211,256,617Metadata aware copyback for memory devices202211,204,828Management of corruptive read in memory systems202111,146,291Configuring iterative error correction parameters using criteria from previous iterations2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to MICRON TECHNOLOGY INC (46)· patent assignee history
2021–2026Based in US· patent location history
2022–2023Patents assigned to SEAGATE TECHNOLOGY LLC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 46 | 2021–2026 |
| SEAGATE TECHNOLOGY LLC | 2 | 2022–2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 48 | 2021–2026 |