Inventor

Er-Xuan Ping

Inventor

Meridian, ID, US

Overview

1998–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 175 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices24%

H10BElectronic memory devices20%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%

C23CCoating metallic material10%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%

H01LSemiconductor devices4%

H10NElectric solid-state devices not otherwise provided for3%

C30BSingle-crystal growth2%

G11CStatic stores2%

PatentTitleYear

10,943,779Method and system for three-dimensional (3D) structure fill2021 10,879,177PVD deposition and anneal of multi-layer metal-dielectric film2020 10,714,388Method and apparatus for depositing cobalt in a feature2020 10,700,087Multi-layer stacks for 3D NAND extendibility2020 10,446,392Self-aligned nanodots for 3D NAND flash memory2019 10,410,864Hybrid carbon hardmask for lateral hardmask recess reduction2019 10,157,787Method and apparatus for depositing cobalt in a feature2018 9,991,118Hybrid carbon hardmask for lateral hardmask recess reduction2018 9,879,341'Method and apparatus for microwave assisted chalcogen radicals generation for 2-D materials'2018 9,812,328'Methods for forming low resistivity interconnects'2017 9,685,536'Vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain'2017 9,570,307'Methods of doping substrates with ALD'2017 9,530,674'Method and system for three-dimensional (3D) structure fill'2016 9,218,973'Methods of doping substrates with ALD'2015 9,217,209'Methods for epitaxial silicon growth'2015 9,023,723'Method of fabricating a gate-all-around word line for a vertical channel DRAM'2015 9,011,973'Methods for depositing oxygen deficient metal films'2015 8,895,432'Method of fabricating a self-aligned buried bit line for a vertical channel DRAM'2014 8,866,124'Diodes with native oxide regions for use in memory arrays and methods of forming the same'2014 8,735,292'Semiconductor processing methods'2014 8,633,528'Methods and apparatus for increasing memory density using diode layer sharing'2014 8,569,730'Carbon-based interface layer for a memory device and methods of forming the same'2013 8,551,855'Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same'2013 8,518,184'Methods and systems for controlling temperature during microfeature workpiece processing, E.G., CVD deposition'2013 8,481,396'Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same'2013 8,471,360'Memory cell with carbon switching material having a reduced cross-sectional area and methods for forming the same'2013 8,470,646'Modulation of resistivity in carbon-based read-writeable materials'2013 8,440,567'Semiconductor processing methods'2013 8,421,050'Electronic devices including carbon nano-tube films having carbon-based liners, and methods of forming the same'2013 8,384,192'Methods for forming small-scale capacitor structures'2013 8,309,415'Methods and apparatus for increasing memory density using diode layer sharing'2012 8,232,167'Applying epitaxial silicon in disposable spacer flow'2012 8,152,918'Methods for epitaxial silicon growth'2012 8,120,124'Ultra thin TCS (SiCl4) cell nitride for DRAM capacitor with DCS (SiH2Cl2) interface seeding layer'2012 8,105,867'Self-aligned three-dimensional non-volatile memory fabrication'2012 8,093,123'Integration methods for carbon films in two- and three-dimensional memories formed therefrom'2012 8,048,474'Method of making nonvolatile memory cell containing carbon resistivity switching as a storage element by low temperature processing'2011 8,023,310'Nonvolatile memory cell including carbon storage element formed on a silicide layer'2011 8,013,371'Ultra thin TCS (SiCl4) cell nitride for DRAM capacitor with DCS (SiH2Cl2) interface seeding layer'2011 7,989,864'Methods for enhancing capacitors having roughened features to increase charge-storage capacity'2011 7,969,011'MIIM diodes having stacked structure'2011 7,923,322'Method of forming a capacitor'2011 7,915,168'Semiconductor processing methods'2011 7,906,393'Methods for forming small-scale capacitor structures'2011 7,884,427'Applying epitaxial silicon in disposable spacer flow'2011 7,830,698'Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same'2010 7,771,537'Methods and systems for controlling temperature during microfeature workpiece processing, E.G. CVD deposition'2010 7,723,180'Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same'2010 7,704,884'Semiconductor processing methods'2010 7,647,886'Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers'2010 7,625,795'Container capacitor structure and method of formation thereof'2009 7,579,232'Method of making a nonvolatile memory device including forming a pillar shaped semiconductor device and a shadow mask'2009 7,579,235'Container capacitor structure and method of formation thereof'2009 7,576,380'Methods for enhancing capacitors having roughened features to increase charge-storage capacity'2009 7,528,430'Electronic systems'2009 7,528,435'Semiconductor constructions'2009 7,440,255'Capacitor constructions and methods of forming'2008 7,422,635'Methods and apparatus for processing microfeature workpieces, e.g., for depositing materials on microfeature workpieces'2008 7,405,438'Capacitor constructions and semiconductor structures'2008 7,355,232'Memory devices with dual-sided capacitors'2008 7,344,755'Methods and apparatus for processing microfeature workpieces; methods for conditioning ALD reaction chambers'2008 7,342,273'Applying epitaxial silicon in disposable spacer flow'2008 7,321,148'Capacitor constructions and rugged silicon-containing surfaces'2008 7,317,220'Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth'2008 7,279,398'Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces'2007 7,268,382'DRAM cells'2007 7,258,892'Methods and systems for controlling temperature during microfeature workpiece processing, e.g., CVD deposition'2007 7,247,581'Methods for treating pluralities of discrete semiconductor substrates'2007 7,244,648'Methods of forming semiconductor constructions'2007 7,238,613'Diffusion-enhanced crystallization of amorphous materials to improve surface roughness'2007 7,235,138'Microfeature workpiece processing apparatus and methods for batch deposition of materials on microfeature workpieces'2007 7,220,312'Methods for treating semiconductor substrates'2007 7,199,017'Methods of forming semiconductor circuitry'2007 7,183,208'Methods for treating pluralities of discrete semiconductor substrates'2007 7,176,109'Method for forming raised structures by controlled selective epitaxial growth of facet using spacer'2007 7,148,118'Methods of forming metal nitride, and methods of forming capacitor constructions'2006 7,119,369'FET having epitaxial silicon growth'2006 7,112,544'Method of atomic layer deposition on plural semiconductor substrates simultaneously'2006 7,101,756'Methods for enhancing capacitors having roughened features to increase charge-storage capacity'2006 7,101,435'Methods for epitaxial silicon growth'2006 7,090,815'Nanometer engineering of metal-support catalysts'2006 7,071,056'Method of forming a dual-sided capacitor'2006 7,056,806'Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces'2006 7,049,231'Methods of forming capacitors'2006 7,037,775'Applying epitaxial silicon in disposable spacer flow'2006 7,034,353'Methods for enhancing capacitors having roughened features to increase charge-storage capacity'2006 7,023,039'Capacitor structures with dual-sided electrode'2006 7,012,294'Semiconductor constructions'2006 6,979,631'Methods of forming semiconductor circuitry'2005 6,977,407'Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth'2005 6,972,223'Use of atomic oxygen process for improved barrier layer'2005 6,967,132'Methods of forming semiconductor circuitry'2005 6,967,134'Methods of forming nitrogen-containing masses, silicon nitride layers, and capacitor constructions'2005 6,951,636'Nanometer engineering of metal-support catalysts'2005 6,949,427'Methods of forming a capacitor structure'2005 6,943,078'Method and structure for reducing leakage current in capacitors'2005 6,930,015'Diffusion-enhanced crystallization of amorphous materials to improve surface roughness'2005 6,919,638'Method, structure and process flow to reduce line-line capacitance with low-K material'2005 6,916,723'Methods of forming rugged semiconductor-containing surfaces'2005 6,911,367'Methods of forming semiconductive materials having flattened surfaces; methods of forming isolation regions; and methods of forming elevated source/drain regions'2005 6,894,310'Semiconductor constructions comprising monocrystalline silicon together with semiconductive materials comprising elements other than silicon'2005 6,890,818'Methods of forming semiconductor capacitors and memory devices'2005 6,888,186'Reduction of damage in semiconductor container capacitors'2005 6,881,652'Method to fabricate an intrinsic polycrystalline silicon film'2005 6,881,682'Method and structure for reducing leakage current in capacitors'2005 6,870,210'Dual-sided capacitor'2005 6,861,326'Methods of forming semiconductor circuitry'2005 6,858,493'Method of forming a dual-sided capacitor'2005 6,835,674'Methods for treating pluralities of discrete semiconductor substrates'2004 6,797,558'Methods of forming a capacitor with substantially selective deposite of polysilicon on a substantially crystalline capacitor dielectric layer'2004 6,791,138'Use of atomic oxygen process for improved barrier layer'2004 6,791,113'Capacitor constructions comprising a nitrogen-containing layer over a rugged polysilicon layer'2004 6,787,834'Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth'2004 6,756,264'Applying epitaxial silicon in disposable spacer flow'2004 6,756,265'Methods of forming a capacitor structure'2004 6,756,266'Capacitor array structure for semiconductor devices'2004 6,750,172'Nanometer engineering of metal-support catalysts'2004 6,740,574'Methods of forming DRAM assemblies, transistor devices, and openings in substrates'2004 6,716,687'FET having epitaxial silicon growth'2004 6,716,716'Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth'2004 6,703,268'Method to fabricate an intrinsic polycrystalline silicon film'2004 6,704,188'Ultra thin TCS (SiCL4) cell nitride for dram capacitor with DCS (SiH2Cl2) interface seeding layer'2004 6,699,752'Formation of conductive rugged silicon'2004 6,696,715'Method and structure for reducing leakage current in capacitors'2004 6,693,007'Methods of utilizing a sacrificial layer during formation of a capacitor'2004 6,664,198'Method of forming a silicon nitride dielectric layer'2003 6,613,628'Method and structure for reducing leakage current in capacitors'2003 6,607,965'Methods of forming capacitors'2003 6,608,342'Container capacitor structure and method of formation thereof'2003 6,600,207'Structure to reduce line-line capacitance with low K material'2003 6,583,441'Capacitor constructions comprising a nitrogen-containing layer over a rugged polysilicon layer'2003 6,583,006'Method to reduce floating grain defects in dual-sided container capacitor fabrication'2003 6,562,684'Methods of forming dielectric materials'2003 6,551,893'Atomic layer deposition of capacitor dielectric'2003 6,538,274'Reduction of damage in semiconductor container capacitors'2003 6,531,407'Method, structure and process flow to reduce line-line capacitance with low-K material'2003 6,518,117'Methods of forming nitrogen-containing masses, silicon nitride layers, and capacitor constructions'2003 6,518,611'Capacitor array structure for semiconductor devices'2003 6,511,892'Diffusion-enhanced crystallization of amorphous materials to improve surface roughness'2003 6,509,227'Formation of conductive rugged silicon'2003 6,509,239'Method of fabricating a field effect transistor'2003 6,500,744'Methods of forming DRAM assemblies, transistor devices, and openings in substrates'2002 6,498,063'Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth'2002 6,465,373'Ultra thin TCS (SiCl4) cell nitride for DRAM capacitor with DCS (SiH2Cl2) interface seeding layer'2002 6,458,699'Methods of forming a contact to a substrate'2002 6,458,652'Methods of forming capacitor electrodes'2002 6,448,129'Applying epitaxial silicon in disposable spacer flow'2002 6,444,590'Semiconductor processing methods, methods of forming hemispherical grain polysilicon, methods of forming capacitors, and methods of forming wordlines'2002 6,441,494'Microelectronic contacts'2002 6,436,818'Semiconductor structure having a doped conductive layer'2002 6,399,983'Reduction of shorts among electrical cells formed on a semiconductor substrate'2002 6,395,615'Selective silicon formation for semiconductor devices'2002 6,383,886'Method to reduce floating grain defects in dual-sided container capacitor fabrication'2002 6,383,851'Method to fabricate an intrinsic polycrystalline silicon film thin film transistor'2002 6,351,005'Integrated capacitor incorporating high K dielectric'2002 6,350,648'Formation of conductive rugged silicon'2002 6,344,418'Methods of forming hemispherical grain polysilicon'2002 6,329,263'Method of forming a container capacitor structure'2001 6,313,026'Microelectronic contacts and methods for producing same'2001 6,306,774'Method of forming a wordline'2001 6,303,515'Method of forming a capacitor'2001 6,235,605'Selective silicon formation for semiconductor devices'2001 6,204,156'Method to fabricate an intrinsic polycrystalline silicon film'2001 6,169,037'Semiconductor processing methods'2001 6,159,852'Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor'2000 6,159,818'Method of forming a container capacitor structure'2000 6,153,899'Capacitor array structure for semiconductor devices'2000 6,124,164'Method of making integrated capacitor incorporating high K dielectric'2000 6,083,849'Methods of forming hemispherical grain polysilicon'2000 6,069,053'Formation of conductive rugged silicon'2000 6,015,997'Semiconductor structure having a doped conductive layer'2000 5,937,314'Diffusion-enhanced crystallization of amorphous materials to improve surface roughness'1999 5,882,979'Method for forming controllable surface enhanced three dimensional objects'1999 5,851,875'Process for forming capacitor array structure for semiconductor devices'1998 5,721,171'Method for forming controllable surface enhanced three dimensional objects'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2015Patents assigned to MICRON TECHNOLOGY INC (139)· patent assignee history

1998–2011Based in Boise, ID, US· patent location history

2000–2017Based in Meridian, ID, US· patent location history

2004Based in Meridan, ID, US· patent location history

2006–2009Based in Manassas, VA, US· patent location history

2009–2014Patents assigned to SANDISK 3D LLC (17)· patent assignee history

2009–2021Based in Fremont, CA, US· patent location history

2012–2017Patents assigned to PING ER-XUAN (21)· patent assignee history

2012–2013Patents assigned to XU HUIWEN (8)· patent assignee history

2014–2021Patents assigned to APPLIED MATERIALS INC (16)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	139	1998–2015
PING ER-XUANself	21	2012–2017
SANDISK 3D LLC	17	2009–2014
APPLIED MATERIALS INC	16	2014–2021
XU HUIWEN	8	2012–2013

Locations

Location	Patents	Span
Meridian, ID, US	107	2000–2017
Fremont, California, US	37	2009–2021
Boise, ID, US	28	1998–2011
Manassas, Virginia, US	2	2006–2009
Meridan, ID, US	1	2004