Inventor
Chung-Chi Ko
Inventor
Nantou County, TW
Overview
Patents· 76 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1035%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%
H01LSemiconductor devices23%
H10DInorganic electric semiconductor devices7%
B01DSeparation1%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry1%
C23CCoating metallic material1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,867,860Methods of forming FinFET device202010,840,134Interconnect structure and method202010,818,598Methods for reducing dual damascene distortion202010,804,374Spacer structure with high plasma resistance for semiconductor devices202010,748,760Varying temperature anneal for film and structures formed thereby202010,692,773Forming nitrogen-containing low-K gate spacer202010,516,035Semiconductor device structure with a low-k spacer layer and method for manufacturing the same201910,516,036Spacer structure with high plasma resistance for semiconductor devices201910,515,822Method for preventing bottom layer wrinkling in a semiconductor device201910,510,584Via patterning using multiple photo multiple etch201910,510,585Multi-patterning to form vias with straight profiles201910,510,852Low-k feature formation processes and structures formed thereby201910,483,372Spacer structure with high plasma resistance for semiconductor devices201910,340,178Via patterning using multiple photo multiple etch201910,332,836Methods for reducing dual damascene distortion201910,312,107Forming interconnect structure using plasma treated metal hard mask201910,304,677Low-k feature formation processes and structures formed thereby201910,269,627Interconnect structure and method201910,163,691Low-K dielectric interconnect systems201810,163,688Interconnect structure with kinked profile201810,141,220Via patterning using multiple photo multiple etch201810,062,645Interconnect structure for semiconductor devices20189,842,804'Methods for reducing dual damascene distortion'20179,818,638'Manufacturing method of semiconductor device'20179,768,061'Low-k dielectric interconnect systems'20179,754,822'Interconnect structure and method'20179,754,818'Via patterning using multiple photo multiple etch'20179,679,848'Interconnect structure for semiconductor devices'20179,679,804'Multi-patterning to form vias with straight profiles'20179,659,811'Manufacturing method of semiconductor device'20179,640,428'Self-aligned repairing process for barrier layer'20179,589,856'Automatically adjusting baking process for low-k dielectric material'20179,514,928'Selective repairing process for barrier layer'20169,460,997'Interconnect structure for semiconductor devices'20169,412,648'Via patterning using multiple photo multiple etch'20169,324,606'Self-aligned repairing process for barrier layer'20169,236,294'Method for forming semiconductor device structure'20169,196,551'Automatically adjusting baking process for low-k dielectric material'20159,153,538'Semiconductor devices and methods of manufacture thereof'20159,136,226'Impurity doped UV protection layer'20159,130,017'Methods for forming interconnect structures of integrated circuits'20159,093,265'High UV curing efficiency for low-k dielectrics'20159,087,877'Low-k interconnect structures with reduced RC delay'20159,004,914'Method of and apparatus for active energy assist baking'20158,993,435'Low-k Cu barriers in damascene interconnect structures'20158,940,643'Double patterning strategy for contact hole and trench in photolithography'20158,846,528'Method of modifying a low k dielectric layer having etched features and the resulting product'20148,629,056'Method for forming self-assembled mono-layer liner for cu/porous low-k interconnections'20148,536,064'Double patterning strategy for contact hole and trench in photolithography'20138,481,412'Method of and apparatus for active energy assist baking'20138,470,708'Double patterning strategy for contact hole and trench in photolithography'20138,361,900'Barrier layer for copper interconnect'20138,158,521'Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical properties'20128,105,947'Post etch dielectric film re-capping layer'20127,968,451'Method for forming self-assembled mono-layer liner for Cu/porous low-k interconnections'20117,897,505'Method for enhancing adhesion between layers in BEOL fabrication'20117,732,923'Impurity doped UV protection layer'20107,723,226'Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio'20107,598,176'Method for photoresist stripping and treatment of low-k dielectric material'20097,485,949'Semiconductor device'20097,466,027'Interconnect structures with surfaces roughness improving liner and methods for fabricating the same'20087,429,542'UV treatment for low-k dielectric layer in damascene structure'20087,410,895'Methods for forming interconnect structures'20087,312,531'Semiconductor device and fabrication method thereof'20077,250,370'Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical properties'20077,172,964'Method of preventing photoresist poisoning of a low-dielectric-constant insulator'20076,962,869'SiOCH low k surface protection layer formation by CxHy gas plasma treatment'20056,924,242'SiOC properties and its uniformity in bulk for damascene applications'20056,908,773'ATR-FTIR metal surface cleanliness monitoring'20056,867,126'Method to increase cracking threshold for low-k materials'20056,812,043'Method for forming a carbon doped oxide low-k insulating layer'20046,806,185'Method for forming low dielectric constant damascene structure while employing a carbon doped silicon oxide capping layer'20046,756,321'Method for forming a capping layer over a low-k dielectric with improved adhesion and reduced dielectric constant'20046,654,109'System for detecting surface defects in semiconductor wafers'20036,602,779'Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer'20036,602,780'Method for protecting sidewalls of etched openings to prevent via poisoning'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (39)· patent assignee history
2003–2017Based in Hsinchu, TW· patent location history
2004–2020Based in Nantou County, TW· patent location history
2004–2005Based in Tainan, TW· patent location history
2010–2015Based in Nautou, TW· patent location history
2012–2015Patents assigned to KO CHUNG-CHI (13)· patent assignee history
2012–2015Patents assigned to LIN KENG-CHU (10)· patent assignee history
2012–2015Patents assigned to JENG SHWANG-MING (5)· patent assignee history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (38)· patent assignee history
2016–2019Based in Jen Te Hsiang, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 39 | 2003–2016 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 38 | 2015–2020 |
| KO CHUNG-CHIself | 13 | 2012–2015 |
| LIN KENG-CHU | 10 | 2012–2015 |
| JENG SHWANG-MING | 5 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Nantou County, TW | 59 | 2004–2020 |
| Hsinchu, TW | 5 | 2003–2017 |
| Jen Te Hsiang, TW | 3 | 2016–2019 |
| Nautou, TW | 3 | 2010–2015 |
| Tainan, TW | 2 | 2004–2005 |