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Inventor

Jing Zhang

Inventor
Los Altos, CA, US

Overview

48→
Patents
2002–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 48 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Nprimary
H10NElectric solid-state devices not otherwise provided for24%
H01LSemiconductor devices19%
H10BElectronic memory devices15%
G11CStatic stores12%
H10DInorganic electric semiconductor devices6%
B82YSpecific uses or applications of nanostructures5%
H01FMagnets5%
G11BInformation storage based on relative movement between record carrier and transducer3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
RE047975Perpendicular magnetic tunnel junction (pMTJ) with in-plane magneto-static switching-enhancing layer202010,626,032Wastewater treatment device and wastewater treatment method202010,593,727Magnetic memory cell including two-terminal selector device202010,559,624Selector device having asymmetric conductance for memory applications202010,544,799Centrifugal compressor gas-supplementing structure and compressor202010,217,934Method for manufacturing magnetic memory cells201910,177,308Method for manufacturing magnetic memory cells201910,153,017Method for sensing memory element coupled to selector device20189,956,758Zero alcohol offset printing system20189,679,625'Perpendicular magnetic tunnel junction (pMTJ) with in-plane magneto-static switching-enhancing layer'20179,444,039'Spin-transfer torque magnetic random access memory with perpendicular magnetic anisotropy multilayers'20169,419,210'Spin-transfer torque magnetic random access memory with perpendicular magnetic anisotropy multilayers'20169,318,179'Spin-transfer torque magnetic random access memory with perpendicular magnetic anisotropy multilayers'20169,209,390'Memory device having stitched arrays of 4 F2 memory cells'20159,196,332'Perpendicular magnetic tunnel junction (pMTJ) with in-plane magneto-static switching-enhancing layer'20159,166,154'MTJ stack and bottom electrode patterning process with ion beam etching using a single mask'20159,082,695'Vialess memory structure and method of manufacturing same'20159,070,692'Shields for magnetic memory chip packages'20159,070,869'Fabrication method for high-density MRAM using thin hard mask'20159,029,822'High density resistive memory having a vertical dual channel transistor'20159,029,824'Memory device having stitched arrays of 4 F2 memory cells'20159,019,758'Spin-transfer torque magnetic random access memory with perpendicular magnetic anisotropy multilayers'20159,013,045'MRAM with sidewall protection and method of fabrication'20158,981,506'Magnetic random access memory with switchable switching assist layer'20158,975,088'MRAM etching processes'20158,975,089'Method for forming MTJ memory element'20158,962,349'Method of manufacturing magnetic tunnel junction memory element'20158,890,108'Memory device having vertical selection transistors with shared channel structure and method for making the same'20148,883,520'Redeposition control in MRAM fabrication process'20148,860,158'High speed STT-MRAM with orthogonal pinned layer'20148,802,451'Method for manufacturing high density non-volatile magnetic memory'20148,806,284'Method for bit-error rate testing of resistance-based RAM cells using a reflected signal'20148,796,795'MRAM with sidewall protection and method of fabrication'20148,772,888'MTJ MRAM with stud patterning'20148,709,956'MRAM with sidewall protection and method of fabrication'20148,704,206'Memory device including transistor array with shared plate channel and method for making the same'20148,633,720'Method and apparatus for measuring magnetic parameters of magnetic thin film structures'20148,619,391'Magnetic write heads with bi-layer wrap around shields having dissimilar shield layer widths'20138,575,584'Resistive memory device having vertical transistors and method for making the same'20138,574,928'MRAM fabrication method with sidewall cleaning'20138,565,010'Magnetic random access memory with field compensating layer and multi-level cell'20138,536,063'MRAM etching processes'20138,492,860'Magnetic random access memory with switching assist layer'2013D0516165'Pull-down sprayer'20066,989,972'Magnetoresistive sensor with overlapping leads having distributed current'20066,943,993'Magnetic recording head with a side shield structure for controlling side reading of thin film read sensor'20056,934,129'Magnetoresistive sensor with overlapping lead layers including alpha tantalum and conductive layers'20056,447,935'Method and system for reducing assymetry in a spin valve having a synthetic pinned layer'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2006Based in San Jose, CA, US· patent location history
2013–2020Patents assigned to AVALANCHE TECHNOLOGY INC (39)· patent assignee history
2013–2015Patents assigned to ZHANG JING (18)· patent assignee history
2013–2015Patents assigned to HUAI YIMING (16)· patent assignee history
2013–2015Patents assigned to SATOH KIMIHIRO (11)· patent assignee history
2013–2015Patents assigned to RANJAN RAJIV YADAV (8)· patent assignee history
2013–2020Based in Los Altos, CA, US· patent location history
2018Based in Kunming, CN· patent location history
2020Based in Beijing, CN· patent location history
2020Based in Guangdong, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
AVALANCHE TECHNOLOGY INC392013–2020
ZHANG JINGself182013–2015
HUAI YIMING162013–2015
SATOH KIMIHIRO112013–2015
RANJAN RAJIV YADAV82013–2015
Locations
LocationPatentsSpan
Los Altos, California, US402013–2020
San Jose, California, US42002–2006
Beijing, CN12020
Guangdong, CN12020
Kunming, CN12018