LexDanaLexDanabeta
Inventor

Ward D. Parkinson

Inventor
Boise, ID, US

Overview

103→
Patents
1980–2021
Patent span
Physics
Primary field (CPC G)

Patents· 103 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores52%
H10BElectronic memory devices11%
H10NElectric solid-state devices not otherwise provided for8%
G06FElectric digital data processing8%
H05KPrinted circuits4%
H10DInorganic electric semiconductor devices4%
H03KPulse technique3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
F24FAir-conditioning2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
11,099,784Crosspoint memory architecture for high bandwidth operation with small page buffer202110,622,063Phase change memory device with reduced read disturb and method of making the same20209,753,481'NMOS regulated voltage reference'20179,576,648'Method and apparatus for decoding memory'20179,570,163'Immunity of phase change material to disturb in the amorphous phase'20179,536,606'Seasoning phase change memories'20179,472,273'Method and apparatus for decoding memory'20169,251,895'Immunity of phase change material to disturb in the amorphous phase'20169,076,521'Method and apparatus for decoding memory'20159,036,409'Immunity of phase change material to disturb in the amorphous phase'20158,861,293'Immunity of phase change material to disturb in the amorphous phase'20148,792,270'Programmable resistance memory'20148,773,941'Method and apparatus for decoding memory'20148,767,440'Sector array addressing for ECC management'20148,755,216'Programmable resistance memory with feedback control'20148,716,056'Method for forming chalcogenide switch with crystallized thin film diode isolation'20148,705,306'Method for using a bit specific reference level to read a phase change memory'20148,634,226'Immunity of phase change material to disturb in the amorphous phase'20148,566,674'Using a phase change memory as a high volume memory'20138,503,219'Programmable resistance memory with feedback control'20138,441,836'Sector array addressing for ECC management'20138,427,862'Reading a phase change memory'20138,379,439'Programmable matrix array with chalcogenide material'20138,373,151'Write-once memory array including phase-change elements and threshold switch isolation'20138,259,525'Using a bit specific reference level to read a memory'20128,223,580'Method and apparatus for decoding memory'20128,203,872'Method and apparatus for accessing a multi-mode programmable resistance memory'20128,194,433'Method and apparatus for accessing a bidirectional memory'20128,183,565'Programmable resistance memory array with dedicated test cell'20128,130,536'Read window in chalcogenide semiconductor memories'20128,120,943'Accessing a phase change memory'20128,116,159'Using a bit specific reference level to read a resistive memory'20128,098,512'Reading phase change memories'20128,077,498'Reading a phase change memory'20118,036,013'Using higher current to read a triggered phase change memory'20118,018,786'Method for reading semiconductor memories and semiconductor memory'20117,990,761'Immunity of phase change material to disturb in the amorphous phase'20117,983,104'Page mode access for non-volatile memory arrays'20117,961,495'Programmable resistance memory with feedback control'20117,957,207'Programmable resistance memory with interface circuitry for providing read information to external circuitry for processing'20117,936,584'Reading phase change memories'20117,864,567'Programming a normally single phase chalcogenide material for use as a memory of FPLA'20117,849,712'Reading a phase change memory'20107,838,864'Chalcogenide switch with laser recrystallized diode isolation device and use thereof in three dimensional memory arrays'20107,839,674'Programmable matrix array with chalcogenide material'20107,808,807'Method and apparatus for accessing a multi-mode programmable resistance memory'20107,778,064'Accessing a phase change memory'20107,706,178'Programmable matrix array with phase-change material'20107,692,958'Method for reading phase change memories and phase change memory'20107,684,225'Sequential and video access for non-volatile memory arrays'20107,646,630'Programmable matrix array with chalcogenide material'20107,646,626'Page mode access for non-volatile memory arrays'20107,590,918'Using a phase change memory as a high volume memory'20097,499,315'Programmable matrix array with chalcogenide material'20097,495,944'Reading phase change memories'20097,471,552'Analog phase change memory'20087,466,584'Method and apparatus for driving an electronic load'20087,453,715'Reading a phase change memory'20087,426,135'Static random access memory cell using chalcogenide'20087,414,883'Programming a normally single phase chalcogenide material for use as a memory or FPLA'20087,391,664'Page mode access for non-volatile memory arrays'20087,388,775'Detecting switching of access elements of phase change memory cells'20087,365,355'Programmable matrix array with phase-change material'20087,308,067'Read bias scheme for phase change memories'20077,280,390'Reading phase change memories without triggering reset cell threshold devices'20077,271,403'Isolating phase change memory devices'20077,154,774'Detecting switching of access elements of phase change memory cells'20066,990,017'Accessing phase change memories'20066,813,177'Method and system to store information'20046,795,338'Memory having access devices using phase change material such as chalcogenide'20046,781,860'High voltage row and column driver for programmable resistance memory'20046,778,420'Method of operating programmable resistant element'20046,768,665'Refreshing memory cells of a phase change material memory device'20046,545,907'Technique and apparatus for performing write operations to a phase change material memory device'20036,448,628'Chip decoupling capacitor'20026,184,568'Integrated circuit module having on-chip surge capacitors'20016,124,625'Chip decoupling capacitor'20005,949,737'Memory device and method for reading data therefrom'19995,907,512'Mask write enablement for memory devices which permits selective masked enablement of plural segments'19995,831,927'Memory device and method for reading data therefrom'19985,715,208'Memory device and method for reading data therefrom'19985,687,109'Integrated circuit module having on-chip surge capacitors'19975,555,429'Multiport RAM based multiprocessor'19965,475,631'Multiport RAM based multiprocessor'19955,325,331'Improved device for sensing information store in a dynamic memory'19945,307,309'Memory module having on-chip surge capacitors'19945,266,821'Chip decoupling capacitor'19935,173,905'Parity and error correction coding on integrated circuit addresses'19925,159,676'Semi-smart DRAM controller IC to provide a pseudo-cache mode of operation using standard page mode draws'19925,042,011'Sense amplifier pulldown device with tailored edge input'19915,032,530'Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants'19915,021,864'Die-mounting paddle for mechanical stress reduction in plastic IC packages'19914,962,326'Reduced latchup in precharging I/O lines to sense amp signal levels'19904,924,442'Pull up circuit for digit lines in a semiconductor memory'19904,914,631'Pull up circuit for sense lines in a semiconductor memory'19904,897,568'Active up-pump for semiconductor sense lines'19904,527,185'Integrated circuit device and subassembly'19854,454,529'Integrated circuit device having internal dampening for a plurality of power supplies'19844,451,845'Lead frame device including ceramic encapsulated capacitor and IC chip'19844,441,125'Image sensor using dynamic random access memory'19844,337,524'Backup power circuit for biasing bit lines of a static semiconductor memory'19824,223,238'Integrated circuit substrate charge pump'19804,221,977'Static I.sup.2 L ram'1980

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1980Based in Dallas, TX, US· patent location history
1982–2021Based in Boise, ID, US· patent location history
1984–2012Patents assigned to MICRON TECHNOLOGY INC (24)· patent assignee history
2003–2017Patents assigned to OVONYX INC (58)· patent assignee history
2004–2008Patents assigned to INTEL CORP (6)· patent assignee history
2011–2014Patents assigned to PARKINSON WARD D (8)· patent assignee history
2012–2017Patents assigned to PARKINSON WARD (18)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
OVONYX INC582003–2017
MICRON TECHNOLOGY INC241984–2012
PARKINSON WARDself182012–2017
PARKINSON WARD Dself82011–2014
INTEL CORP62004–2008
Locations
LocationPatentsSpan
Boise, ID, US1011982–2021
Dallas, Texas, US21980