Inventor
Jun He
Inventor
Portland, OR, US
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
B23KSoldering or unsoldering7%
G11CStatic stores7%
H01LSemiconductor devices5%
G01RMeasuring electric variables4%
H05KPrinted circuits4%
H10DInorganic electric semiconductor devices4%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry3%
B82YSpecific uses or applications of nanostructures3%
PatentTitleYear
10,119,003Surfactant-based monolithic columns, methods for making the same, and methods for using the same20189,984,922Interconnects having sealing structures to enable selective metal capping layers20189,461,010'Debond interconnect structures'20169,437,545'Interconnects having sealing structures to enable selective metal capping layers'20169,361,702'Image detection method and device'20169,269,686'Debond interconnect structures'20168,928,125'Interconnects having sealing structures to enable selective metal capping layers'20158,704,336'Selective removal of on-die redistribution interconnects from scribe-lines'20148,703,547'Thyristor comprising a special doped region characterized by an LDD region and a halo implant'20148,637,778'Debond interconnect structures'20148,435,410'Surfactant-based monolithic columns, methods for making the same, and method for using the same'20138,368,171'Methods of forming electromigration and thermal gradient based fuse structures'20138,331,186'Fuse programming schemes for robust yield'20128,242,831'Tamper resistant fuse design'20128,058,710'Interconnects having sealing structures to enable selective metal capping layers'20117,889,013'Microelectronic die having CMOS ring oscillator thereon and method of using same'20117,889,587'Fuse programming schemes for robust yield'20117,679,145'Transistor performance enhancement using engineered strains'20107,662,674'Methods of forming electromigration and thermal gradient based fuse structures'20107,544,966'Three-terminal electrical bistable devices'20097,524,754'Interconnect shunt used for current distribution and reliability redundancy'20097,402,509'Method of forming self-passivating interconnects and resulting devices'20087,402,519'Interconnects having sealing structures to enable selective metal capping layers'20087,348,283'Mechanically robust dielectric film and stack'20087,332,741'Multidirectional leakage path test structure'20087,208,830'Interconnect shunt used for current distribution and reliability redundancy'20077,175,970'Mechanically robust interconnect for low-k dielectric material using post treatment'20077,151,051'Interconnect structure for an integrated circuit and method of fabrication'20067,087,452'Edge arrangements for integrated circuit chips'20067,071,554'Stress mitigation layer to reduce under bump stress concentration'20066,998,216'Mechanically robust interconnect for low-k dielectric material using post treatment'20066,998,868'Test key for bridge and continuity testing'20066,919,637'Interconnect structure for an integrated circuit and method of fabrication'20056,838,299'Forming defect prevention trenches in dicing streets'20055,705,824'Field controlled current modulators based on tunable barrier strengths'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2018Patents assigned to INTEL CORP (27)· patent assignee history
2005–2015Based in Portland, OR, US· patent location history
2006–2014Patents assigned to GRACE SEMICONDUCTOR MFG CORP (3)· patent assignee history
2006–2014Based in Shanghai, CN· patent location history
2011–2016Patents assigned to HE JUN (10)· patent assignee history
2011–2015Patents assigned to FISCHER KEVIN J (2)· patent assignee history
2012Patents assigned to CHEN ZHANPING (2)· patent assignee history
2013–2018Based in Atlanta, GA, US· patent location history
2016–2018Based in Phoenix, AZ, US· patent location history
2016Based in Shenzhen, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 27 | 2005–2018 |
| HE JUNself | 10 | 2011–2016 |
| GRACE SEMICONDUCTOR MFG CORP | 3 | 2006–2014 |
| CHEN ZHANPING | 2 | 2012 |
| FISCHER KEVIN J | 2 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 23 | 2005–2015 |
| Phoenix, AZ, US | 4 | 2016–2018 |
| Shanghai, CN | 4 | 2006–2014 |
| Atlanta, Georgia, US | 2 | 2013–2018 |
| Shenzhen, CN | 1 | 2016 |