Inventor
Scott A. Bell
Inventor
San Jose, CA, US
Overview
Patents· 104 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1036%
H10DInorganic electric semiconductor devices25%
H10BElectronic memory devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
H01LSemiconductor devices5%
B65DContainers for storage or transport of articles or materials, e.g. bags, barrels, bottles, boxes, cans, cartons, crates, drums, jars, tanks, hoppers, forwarding containers1%
C23CCoating metallic material1%
PatentTitleYear
10,593,688Split-gate semiconductor device with L-shaped gate202010,020,316Split-gate semiconductor device with L-shaped gate20189,735,289'Ion implantation-assisted etch-back process for improving spacer shape and spacer width control'20179,673,206'Buried hard mask for embedded semiconductor device patterning'20179,589,805'Split-gate semiconductor device with L-shaped gate'20179,466,496'Spacer formation with straight sidewall'20169,431,503'Integrating transistors with different poly-silicon heights on the same die'20169,318,498'Buried hard mask for embedded semiconductor device patterning'20169,252,221'Formation of gate sidewall structure'20168,901,720'Method for forming narrow structures in a semiconductor device'20148,815,727'Integrated circuit with metal and semi-conducting gate'20148,652,907'Integrating transistors with different poly-silicon heights on the same die'20148,629,535'Mask for forming integrated circuit'20148,384,146'Methods for forming a memory cell having a top oxide spacer'20138,283,718'Integrated circuit system with metal and semi-conducting gate'20128,202,779'Methods for forming a memory cell having a top oxide spacer'20127,928,005'Method for forming narrow structures in a semiconductor device'20117,675,104'Integrated circuit memory system employing silicon rich layers'20107,659,166'Integration approach to form the core floating gate for flash memory using an amorphous carbon hard mask and ArF lithography'20107,521,304'Method for forming integrated circuit'20097,498,222'Enhanced etching of a high dielectric constant layer'20097,465,644'Isolation region bird\'s beak suppression'20087,368,225'Two mask photoresist exposure pattern for dense and isolated regions'20087,361,588'Etch process for CD reduction of arc material'20087,285,499'Polymer spacers for creating sub-lithographic spaces'20077,268,066'Method for semiconductor gate line dimension reduction'20077,122,455'Patterning with rigid organic under-layer'20067,084,071'Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon'20067,077,291'Package assembly with foamed topping'20067,052,921'System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process'20067,005,386'Method for reducing resist height erosion in a gate etch process'20066,989,332'Ion implantation to modulate amorphous carbon stress'20066,900,002'Antireflective bi-layer hardmask including a densified amorphous carbon layer'20056,884,733'Use of amorphous carbon hard mask for gate patterning to eliminate requirement of poly re-oxidation'20056,875,668'Notched gate structure fabrication'20056,864,556'CVD organic polymer film for advanced gate patterning'20056,855,627'Method of using amorphous carbon to prevent resist poisoning'20056,849,530'Method for semiconductor gate line dimension reduction'20056,803,178'Two mask photoresist exposure pattern for dense and isolated regions'20046,797,552'Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices'20046,773,998'Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning'20046,764,947'Method for reducing gate line deformation and reducing gate line widths in semiconductor devices'20046,764,949'Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication'20046,753,266'Method of enhancing gate patterning properties with reflective hard mask'20046,750,127'Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance'20046,740,566'Ultra-thin resist shallow trench process using high selectivity nitride etch'20046,737,222'Dual damascene process utilizing a bi-layer imaging layer'20046,689,541'Process for forming a photoresist mask'20046,664,154'Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes'20036,660,645'Process for etching an organic dielectric using a silyated photoresist mask'20036,653,190'Flash memory with controlled wordline width'20036,642,148'RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist'20036,642,152'Method for ultra thin resist linewidth reduction using implantation'20036,635,409'Method of strengthening photoresist to prevent pattern collapse'20036,627,360'Carbonization process for an etch mask'20036,620,717'Memory with disposable ARC for wordline formation'20036,606,738'Analytical model for predicting the operating process window for lithographic patterning techniques based on photoresist trim technology'20036,605,514'Planar finFET patterning using amorphous carbon'20036,596,553'Method of pinhole decoration and detection'20036,566,214'Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer'20036,563,221'Connection structures for integrated circuits and processes for their formation'20036,548,423'Multilayer anti-reflective coating process for integrated circuit fabrication'20036,544,885'Polished hard mask process for conductor layer patterning'20036,541,360'Bi-layer trim etch process to form integrated circuit gate structures'20036,534,418'Use of silicon containing imaging layer to define sub-resolution gate structures'20036,514,871'Gate etch process with extended CD trim capability'20036,500,756'Method of forming sub-lithographic spaces between polysilicon lines'20026,458,606'Etch bias distribution across semiconductor wafer'20026,440,640'Thin resist with transition metal hard mask for via etch application'20026,423,457'In-situ process for monitoring lateral photoresist etching'20026,420,097'Hardmask trim process'20026,383,952'RELACS process to double the frequency or pitch of small feature formation'20026,380,588'Semiconductor device having uniform spacers'20026,340,603'Plasma emission detection during lateral processing of photoresist mask'20026,323,093'Process for fabricating a semiconductor device component by oxidizing a silicon hard mask'20016,309,926'Thin resist with nitride hard mask for gate etch application'20016,306,710'Fabrication of a gate structures having a longer length toward the top for formation of a rectangular shaped spacer'20016,306,560'Ultra-thin resist and SiON/oxide hard mask for metal etch'20016,287,918'Process for fabricating a metal semiconductor device component by lateral oxidization'20016,262,435'Etch bias distribution across semiconductor wafer'20016,214,683'Process for fabricating a semiconductor device component using lateral metal oxidation'20016,211,044'Process for fabricating a semiconductor device component using a selective silicidation reaction'20016,200,907'Ultra-thin resist and barrier metal/oxide hard mask for metal etch'20016,184,128'Method using a thin resist mask for dual damascene stop layer etch'20016,171,763'Ultra-thin resist and oxide/nitride hard mask for metal etch'20016,165,695'Thin resist with amorphous silicon hard mask for via etch application'20006,162,587'Thin resist with transition metal hard mask for via etch application'20006,156,658'Ultra-thin resist and silicon/oxide hard mask for metal etch'20006,140,023'Method for transferring patterns created by lithography'20006,133,129'Method for fabricating a metal structure with reduced length that is beyond photolithography limitations'20006,127,070'Thin resist with nitride hard mask for via etch application'20006,121,123'Gate pattern formation using a BARC as a hardmask'20006,121,155'Integrated circuit fabrication critical dimension control using self-limiting resist etch'20006,107,172'Controlled linewidth reduction during gate pattern formation using an SiON BARC'20006,103,611'Methods and arrangements for improved spacer formation within a semiconductor device'20006,060,377'Method for fabricating a polysilicon structure with reduced length that is beyond photolithography limitations'20006,020,269'Ultra-thin resist and nitride/oxide hard mask for metal etch'20005,990,524'Silicon oxime spacer for preventing over-etching during local interconnect formation'19995,965,461'Controlled linewidth reduction during gate pattern formation using a spin-on barc'19995,963,841'Gate pattern formation using a bottom anti-reflective coating'19995,885,902'Integrated arc and polysilicon etching process'19995,879,975'Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile'19995,767,018'Method of etching a polysilicon pattern'19985,763,327'Integrated arc and polysilicon etching process'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2014Patents assigned to ADVANCED MICRO DEVICES INC (88)· patent assignee history
1998–2020Based in San Jose, CA, US· patent location history
2006–2014Patents assigned to BELL SCOTT A (3)· patent assignee history
2006Based in Redondo Beach, CA, US· patent location history
2008–2016Patents assigned to SPANSION LLC (12)· patent assignee history
2012–2014Patents assigned to BELL SCOTT (3)· patent assignee history
2016–2020Patents assigned to CYPRESS SEMICONDUCTOR CORP (9)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 88 | 1998–2014 |
| SPANSION LLC | 12 | 2008–2016 |
| CYPRESS SEMICONDUCTOR CORP | 9 | 2016–2020 |
| BELL SCOTTself | 3 | 2012–2014 |
| BELL SCOTT Aself | 3 | 2006–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 103 | 1998–2020 |
| Redondo Beach, California, US | 1 | 2006 |