Inventor
Sohrab Kianian
Inventor
Los Altos Hills, CA, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices44%
H10DInorganic electric semiconductor devices28%
G11CStatic stores22%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes3%
G07FCoin-freed or like apparatus3%
PatentTitleYear
7,547,603'Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same'20097,537,996'Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate'20097,533,063'Smart memory card wallet'20097,411,246'Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby'20087,326,614'Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby'20087,307,308'Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation'20077,205,198'Method of making a bi-directional read/program non-volatile floating gate memory cell'20077,190,018'Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation'20077,144,778'Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line'20067,129,536'Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same'20067,074,672'Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor'20066,952,033'Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line'20056,952,034'Semiconductor memory array of floating gate memory cells with buried source line and floating gate'20056,940,125'Vertical NROM and methods for making thereof'20056,917,069'Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor'20056,891,220'Method of programming electrons onto a floating gate of a non-volatile memory cell'20056,861,315'Method of manufacturing an array of bi-directional nonvolatile memory cells'20055,852,577'Electrically erasable and programmable read-only memory having a small unit for program and erase'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2009Patents assigned to SILICON STORAGE TECH INC (18)· patent assignee history
1998–2009Based in Los Altos, CA, US· patent location history
2005–2009Based in Los Altos Hills, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SILICON STORAGE TECH INC | 18 | 1998–2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Altos Hills, California, US | 12 | 2005–2009 |
| Los Altos, California, US | 6 | 1998–2009 |