Inventor
Kevin P. Grundy
Inventor
Fremont, CA, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H05KPrinted circuits22%
H01RElectrically-conductive connections19%
G06FElectric digital data processing8%
G01RMeasuring electric variables4%
G11BInformation storage based on relative movement between record carrier and transducer3%
H01CResistors3%
H01GCapacitors3%
H01PWaveguides3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
9,647,318'Modular antenna system'2017D0746798'Indoor antenna'20168,598,696'Multi-surface IC packaging structures'20138,324,727'Low profile discrete electronic components and applications of same'20128,313,333'Connector having a housing with a conductor with a ramp section and a curved surface section'20128,244,993'Memory chain'20128,199,450'ESD protection utilizing radiated thermal relief'20128,079,848'Electrical connector with conductors with a ramp to induce torsion'20118,047,855'High speed, direct path, stair-step, electronic connectors with improved signal integrity characteristics and methods for their manufacture'20118,026,600'Controlled impedance structures for high density interconnections'20117,973,391'Tapered dielectric and conductor structures and applications thereof'20117,966,443'Memory systems including memory devices coupled together in a daisy-chained arrangement'20117,919,355'Multi-surface IC packaging structures and methods for their manufacture'20117,909,615'Torsionally-induced contact-force conductors for electrical connector systems'20117,845,986'Torsionally-induced contact-force conductors for electrical connector systems'20107,837,477'Electrical interconnection devices incorporating Fedundant contact points for reducing capacitive stubs and improved signal integrity'20107,750,446'IC package structures having separate circuit interconnection structures and assemblies constructed thereof'20107,737,545'Multi-surface IC packaging structures and methods for their manufacture'20107,732,904'Multi-surface contact IC packaging structures and assemblies'20107,701,323'Low profile discrete electronic components and applications of same'20107,651,336'High speed, direct path, stair-step, electronic connectors with improved signal integrity characteristics and methods for their manufacture'20107,652,381'Interconnect system without through-holes'20107,651,382'Electrical interconnection devices incorporating redundant contact points for reducing capacitive stubs and improved signal integrity'20107,613,011'Signal-segregating connector system'20097,404,746'Electrical interconnection devices incorporating redundant contact points for reducing capacitive stubs and improved signal integrity'20087,388,279'Tapered dielectric and conductor structures and applications thereof'20087,347,697'Active connector'20087,310,239'IC packaging interposer having controlled impedance or optical interconnections and an integral heat spreader'20077,308,524'Memory chain'20077,279,783'Partitioned integrated circuit package with central clock driver'20077,280,372'Stair step printed circuit board structures for high speed signal transmissions'20077,278,855'High speed, direct path, stair-step, electronic connectors with improved signal integrity characteristics and methods for their manufacture'20077,227,759'Signal-segregating connector system'20077,205,613'Insulating substrate for IC packages having integral ESD protection'20077,192,320'Electrical interconnection devices incorporating redundant contact points for reducing capacitive stubs and improved signal integrity'20077,111,108'Memory system having a multiplexed high-speed channel'20067,061,096'Multi-surface IC packaging structures and methods for their manufacture'20066,600,739'Method and apparatus for switching among a plurality of universal serial bus host devices'20036,330,235'Method and apparatus providing data communication over an existing telephone network without interfering with normal telephony functions'20016,253,250'Method and apparatus for bridging a plurality of buses and handling of an exception event to provide bus isolation'20015,784,571'Method for reducing the bandwidth requirement in a system including a video decoder and a video encoder'19984,924,327'System and method for improving the performance of high-density data storage media'19904,924,330'System and method for improving the performance of high-density data storage media'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990Based in San Jose, CA, US· patent location history
1998–2017Based in Fremont, CA, US· patent location history
2006–2007Patents assigned to SILICON PIPE INC (8)· patent assignee history
2008–2012Patents assigned to INTERCONNECT PORTFOLIO LLC (14)· patent assignee history
2010–2013Patents assigned to SAMSUNG ELECTRONICS CO LTD (10)· patent assignee history
2011–2013Patents assigned to GRUNDY KEVIN P (6)· patent assignee history
2011–2013Patents assigned to FJELSTAD JOSEPH C (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTERCONNECT PORTFOLIO LLC | 14 | 2008–2012 |
| SAMSUNG ELECTRONICS CO LTD | 10 | 2010–2013 |
| SILICON PIPE INC | 8 | 2006–2007 |
| GRUNDY KEVIN Pself | 6 | 2011–2013 |
| FJELSTAD JOSEPH C | 5 | 2011–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 41 | 1998–2017 |
| San Jose, California, US | 2 | 1990 |