Inventor
Tat-Sing P. Chow
Inventor
Schenectady, NY, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices52%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
C23CCoating metallic material3%
H01LSemiconductor devices3%
PatentTitleYear
9,922,838'Selective, electrochemical etching of a semiconductor'20188,350,293'Field effect transistor and method of manufacturing the same'20138,188,514'Transistor'20128,159,024'High voltage (>100V) lateral trench power MOSFET with low specific-on-resistance'20127,144,797'Semiconductor device having multiple-zone junction termination extension, and method for fabricating the same'20066,656,774'Method to enhance operating characteristics of FET, IGBT, and MCT structures'20035,814,859'Self-aligned transistor device including a patterned refracting dielectric layer'19985,510,281'Method of fabricating a self-aligned DMOS transistor device using SiC and spacers'19964,998,151'Power field effect devices having small cell size and low contact resistance'19914,901,127'Circuit including a combined insulated gate bipolar transistor/MOSFET'19904,862,242'Semiconductor wafer with an electrically-isolated semiconductor device'19894,823,176'Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area'19894,801,986'Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method'19894,717,679'Minimal mask process for fabricating a lateral insulated gate semiconductor device'19884,620,211'Method of reducing the current gain of an inherent bipolar transistor in an insulated-gate semiconductor device and resulting devices'19864,429,011'Composite conductive structures and method of making same'19844,333,965'Method of making integrated circuits'19824,227,944'Methods of making composite conductive structures in integrated circuits'1980Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1980–1998Patents assigned to GEN ELECTRIC (12)· patent assignee history
1980–2003Based in Schenectady, NY, US· patent location history
2003Patents assigned to FAIRCHILD SEMICONDUCTOR (1)· patent assignee history
2006–2018Patents assigned to RENSSELAER POLYTECH INST (4)· patent assignee history
2006–2018Based in Niskayuna, NY, US· patent location history
2012–2013Patents assigned to CHOW TAT-SING PAUL (3)· patent assignee history
2013Patents assigned to FURUKAWA ELECTRIC CO LTD (1)· patent assignee history
2013Based in Troy, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GEN ELECTRIC | 12 | 1980–1998 |
| RENSSELAER POLYTECH INST | 4 | 2006–2018 |
| CHOW TAT-SING PAULself | 3 | 2012–2013 |
| FAIRCHILD SEMICONDUCTOR | 1 | 2003 |
| FURUKAWA ELECTRIC CO LTD | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Schenectady, New York, US | 13 | 1980–2003 |
| Niskayuna, New York, US | 4 | 2006–2018 |
| Troy, New York, US | 1 | 2013 |