Inventor

Graham R. Wolstenholme

Inventor

Boise, ID, US

Overview

1994–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 67 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices32%

H10DInorganic electric semiconductor devices16%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%

H10NElectric solid-state devices not otherwise provided for8%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

H01LSemiconductor devices6%

G11CStatic stores3%

Y10TTechnical subjects covered by former us classification2%

A63HToys, e.g. tops, dolls, hoops or building blocks1%

PatentTitleYear

10,879,175Memory devices including stair step or tiered structures and related methods2020 10,748,811Memory devices and related methods2020 10,381,086Multiple blocks per string in 3D NAND memory2019 10,290,581Methods of forming conductive structures including stair step or tiered structures having conductive portions2019 10,269,626Stair step formation using at least two masks2019 9,941,209Conductive structures, systems and devices including conductive structures and related methods2018 9,870,941'Stair step formation using at least two masks'2018 9,786,375'Multiple blocks per string in 3D NAND memory'2017 9,553,099'Pillar arrangement in NAND memory'2017 9,508,731'Pillar arrangement in NAND memory'2016 9,508,591'Stair step formation using at least two masks'2016 9,082,772'Stair step formation using at least two masks'2015 8,609,536'Stair step formation using at least two masks'2013 8,508,999'Vertical NAND memory'2013 8,035,189'Semiconductor constructions'2011 8,034,716'Semiconductor structures including vertical diode structures and methods for making the same'2011 7,781,860'Semiconductor constructions, and electronic systems'2010 7,569,468'Method for forming a floating gate memory with polysilicon local interconnects'2009 7,563,679'Reduction of field edge thinning in peripheral devices'2009 7,563,666'Semiconductor structures including vertical diode structures and methods of making the same'2009 7,517,749'Method for forming an array with polysilicon local interconnects'2009 7,473,615'Semiconductor processing methods'2009 7,279,725'Vertical diode structures'2007 7,271,438'Self-aligned silicide for word lines and contacts'2007 7,262,102'Reduction of field edge thinning in peripheral devices'2007 7,241,662'Reduction of field edge thinning in peripheral devices'2007 7,170,103'Wafer with vertical diode structures'2007 7,166,875'Vertical diode structures'2007 7,115,509'Method for forming polysilicon local interconnects'2006 7,091,549'Programmable memory devices supported by semiconductor substrates'2006 6,949,792'Stacked gate region of a memory cell in a memory device'2005 6,939,764'Methods of forming memory cells having self-aligned silicide'2005 6,873,005'Programmable memory devices supported by semiconductor substrates'2005 6,808,989'Self-aligned floating gate flash cell system and method'2004 6,803,624'Programmable memory devices supported by semiconductive substrates'2004 6,787,401'Method of making vertical diode structures'2004 6,784,046'Method of making vertical diode structures'2004 6,777,291'Methods of forming programmable memory devices comprising tungsten'2004 6,759,708'Stacked gate region of a nonvolatile memory cell for a computer'2004 6,750,091'Diode formation method'2004 6,740,552'Method of making vertical diode structures'2004 6,713,346'Methods of forming a line of flash memory cells'2004 6,692,328'Electronic toy using prerecorded messages'2004 6,690,051'FLASH memory circuitry'2004 6,674,145'Flash memory circuitry'2004 6,653,195'Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell'2003 6,649,968'Flash memory cells'2003 6,624,022'Method of forming FLASH memory'2003 6,429,449'Three-dimensional container diode for use with multi-state material in a non-volatile memory cell'2002 6,406,959'Method of forming FLASH memory, method of forming FLASH memory and SRAM circuitry, and etching methods'2002 6,236,059'Memory cell incorporating a chalcogenide element and method of making same'2001 6,194,746'Vertical diode structures with low series resistance'2001 6,153,890'Memory cell incorporating a chalcogenide element'2000 6,118,135'Three-dimensional container diode for use with multi-state material in a non-volatile memory cell'2000 6,111,264'Small pores defined by a disposable internal spacer for use in chalcogenide memories'2000 5,998,244'Memory cell incorporating a chalcogenide element and method of making same'1999 5,985,698'Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell'1999 5,970,336'Method of making memory cell incorporating a chalcogenide element'1999 5,854,102'Vertical diode structures with low series resistance'1998 5,831,276'Three-dimensional container diode for use with multi-state material in a non-volatile memory cell'1998 5,814,527'Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories'1998 5,751,012'Polysilicon pillar diode for use in a non-volatile memory cell'1998 5,512,504'Method of making a memory array with field oxide islands eliminated'1996 5,496,754'Method for preventing bit line-to-bit line leakage in the access transistor region of an AMG EPROM'1996 5,422,844'Memory array with field oxide islands eliminated and method'1995 5,397,725'Method of controlling oxide thinning in an EPROM or flash memory array'1995 5,319,593'Memory array with field oxide islands eliminated and method'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–1996Patents assigned to NAT SEMICONDUCTOR CORP (5)· patent assignee history

1994Based in Redwood City, CA, US· patent location history

1995–2020Based in Boise, ID, US· patent location history

1998–2020Patents assigned to MICRON TECHNOLOGY INC (56)· patent assignee history

2013–2019Patents assigned to INTEL CORP (5)· patent assignee history

2013Patents assigned to HA CHANG WAN (1)· patent assignee history

2013Patents assigned to LIU ZENGTAO (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	56	1998–2020
INTEL CORP	5	2013–2019
NAT SEMICONDUCTOR CORP	5	1994–1996
HA CHANG WAN	1	2013
LIU ZENGTAO	1	2013

Locations

Location	Patents	Span
Boise, ID, US	66	1995–2020
Redwood City, California, US	1	1994