LexDanaLexDanabeta
Inventor

Ming-Chou Ho

Inventor
Hsinchu, TW

Overview

21→
Patents
1998–2012
Patent span
Electricity
Primary field (CPC H)

Patents· 21 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores47%
H10BElectronic memory devices31%
H10DInorganic electric semiconductor devices22%
PatentTitleYear
8,089,798'Method for operating one-time programmable read-only memory'20127,768,059'Nonvolatile single-poly memory device'20107,447,082'Method for operating single-poly non-volatile memory device'20087,433,243'Operation method of non-volatile memory'20086,920,067'Integrated circuit embedded with single-poly non-volatile memory'20056,914,825'Semiconductor memory device having improved data retention'20056,842,374'Method for operating N-channel electrically erasable programmable logic device'20056,822,286'Cmos-compatible read only memory and method for fabricating the same'20046,812,083'Fabrication method for non-volatile memory'20046,740,556'Method for forming EPROM with low leakage'20046,617,637'Electrically erasable programmable logic device'20036,417,046'Modified nitride spacer for solving charge retention issue in floating gate memory cell'20026,303,454'Process for a snap-back flash EEPROM cell'20016,117,732'Use of a metal contact structure to increase control gate coupling capacitance for a single polysilicon non-volatile memory cell'20006,055,183'Erase method of flash EEPROM by using snapback characteristic'20006,049,484'Erase method to improve flash EEPROM endurance by combining high voltage source erase and negative gate erase'20005,949,717'Method to improve flash EEPROM cell write/erase threshold voltage closure'19995,903,499'Method to erase a flash EEPROM using negative gate source erase followed by a high negative gate erase'19995,862,078'Mixed mode erase method to improve flash eeprom write/erase threshold closure'19995,838,618'Bi-modal erase method for eliminating cycling-induced flash EEPROM cell write/erase threshold closure'19985,726,933'Clipped sine shaped waveform to reduce the cycling-induced electron trapping in the tunneling oxide of flash EEPROM'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2002Patents assigned to TAIWAN SEMICONDUCTOR MFG (10)· patent assignee history
1998–2001Based in Taichung, TW· patent location history
2000Based in Taichang, TW· patent location history
2002–2012Based in Hsinchu, TW· patent location history
2003–2012Patents assigned to EMEMORY TECHNOLOGY INC (11)· patent assignee history
2012Patents assigned to CHING WEN-HAO (1)· patent assignee history
2012Patents assigned to HO MING-CHOU (1)· patent assignee history
2012Patents assigned to HUANG SHAO-CHANG (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
EMEMORY TECHNOLOGY INC112003–2012
TAIWAN SEMICONDUCTOR MFG101998–2002
CHING WEN-HAO12012
HO MING-CHOUself12012
HUANG SHAO-CHANG12012
Locations
LocationPatentsSpan
Hsinchu, TW122002–2012
Taichung, TW81998–2001
Taichang, TW12000