Inventor
WENYU XU
Inventor
US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices31%
H10DInorganic electric semiconductor devices30%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
B82YSpecific uses or applications of nanostructures9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
H10BElectronic memory devices3%
H10NElectric solid-state devices not otherwise provided for3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
LOC211%
PatentTitleYear
12,520,567Hybrid-channel nano-sheet FETs202612,513,980Stacked vertical transport field effect transistor with anchors2025D1102532Decompression toy202512,362,168Solvent annealing of an organic planarization layer202511,942,557Nanosheet transistor with enhanced bottom isolation202411,916,143Vertical transport field-effect transistor with gate patterning202411,908,937Vertical transport field-effect transistor with ring-shaped wrap-around contact202411,849,647Nonmetallic liner around a magnetic tunnel junction202311,843,031Short gate on active and longer gate on STI for nanosheets202311,798,852Hybrid-channel nano-sheet FETs202311,764,259Vertical field-effect transistor with dielectric fin extension202311,735,658Tunnel field-effect transistor with reduced subthreshold swing202311,728,340Single diffusion break isolation for gate-all-around field-effect transistor devices202311,705,517Nanosheet transistors with strained channel regions202311,664,422Nanosheet transistor with ultra low-k spacer and improved patterning robustness202311,637,041Method of forming high mobility complementary metal-oxide-semiconductor (CMOS) devices with fins on insulator202311,621,348Vertical transistor devices with composite high-K and low-K spacers with a controlled top junction202311,575,042Tunnel field-effect transistor with reduced subthreshold swing202311,575,022Vertical field-effect transistor late gate recess process with improved inter-layer dielectric protection202311,569,229Stacked vertical transport field effect transistors with anchors202311,515,401Vertical fin field effect transistor with a reduced gate-to-bottom source/drain parasitic capacitance202211,495,673Vertical fin field effect transistor with a reduced gate-to-bottom source/drain parasitic capacitance202211,430,864VFET device with controllable top spacer202211,276,612Hybrid-channel nano-sheet FETS202211,196,0013D ReRAM formed by metal-assisted chemical etching with replacement wordline and wordline separation202111,183,389Fin field effect transistor devices with self-aligned gates202111,164,940Method of forming III-V on insulator structure on semiconductor substrate2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to IBM (23)· patent assignee history
2021–2026Based in US· patent location history
2022Patents assigned to TESSERA INC (1)· patent assignee history
2023Patents assigned to TESSERA LLC (1)· patent assignee history
2025Patents assigned to SCREEN SPE USA LLC (1)· patent assignee history
2025Based in CN· patent location history
2026Patents assigned to ADEIA SEMICONDUCTOR SOLUTIONS LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 23 | 2021–2025 |
| ADEIA SEMICONDUCTOR SOLUTIONS LLC | 1 | 2026 |
| SCREEN SPE USA LLC | 1 | 2025 |
| TESSERA INC | 1 | 2022 |
| TESSERA LLC | 1 | 2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 26 | 2021–2026 |
| CN | 1 | 2025 |