Inventor
Qiuxia Xu
Inventor
Beijing, CN
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices46%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H01LSemiconductor devices23%
B82YSpecific uses or applications of nanostructures2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
H04LTransmission of digital information, e.g. telegraphic communication1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,068,990Method of manufacturing MOS transistor with stack of cascaded nanowires201810,056,261P type MOSFET20189,934,975N-type MOSFET and method for manufacturing the same20189,899,270'Methods for manufacturing semiconductor devices'20189,548,387'Semiconductor device and method of manufacturing the same'20179,391,073'FinFET device and method for manufacturing the same'20169,384,986'Dual-metal gate CMOS devices and method for manufacturing the same'20169,373,622'CMOS device with improved accuracy of threshold voltage adjustment and method for manufacturing the same'20169,312,187'Semiconductor device and method of manufacturing the same'20169,281,398'Semiconductor structure and method for manufacturing the same'20169,276,085'Semiconductor structure and method for manufacturing the same'20169,252,059'Method for manufacturing semiconductor device'20169,196,706'Method for manufacturing P-type MOSFET'20159,136,181'Method for manufacturing semiconductor device'20159,049,061'CMOS device and method for manufacturing the same'20159,029,225'Method for manufacturing N-type MOSFET'20158,994,119'Semiconductor device with gate stacks having stress and method of manufacturing the same'20158,932,927'Semiconductor structure and method for manufacturing the same'20158,895,374'Semiconductor field-effect transistor structure and method for manufacturing the same'20148,822,292'Method for forming and controlling molecular level SiO2 interface layer'20148,786,032'P-type semiconductor device and method for manufacturing the same'20148,778,744'Method for manufacturing semiconductor field effect transistor'20148,754,482'Semiconductor device and manufacturing method thereof'20148,748,272'Method of introducing strain into channel and device manufactured by using the method'20148,748,250'Method for integration of dual metal gates and dual high-K dielectrics in CMOS devices'20148,703,617'Method for planarizing interlayer dielectric layer'20148,664,119'Semiconductor device manufacturing method'20148,652,893'Semiconductor device and manufacturing method thereof'20148,652,891'Semiconductor device and method of manufacturing the same'20148,598,002'Method for manufacturing metal gate stack structure in gate-first process'20138,574,977'Method for manufacturing stack structure of PMOS device and adjusting gate work function'20138,530,302'Method for manufacturing CMOS FET'20138,466,028'Method for manufacturing multigate device'20138,389,367'Method for manufacturing a semiconductor device'20138,384,162'Device having adjustable channel stress and method thereof'20138,377,769'Method for integrating replacement gate in semiconductor device'20138,367,558'Method for tuning the work function of a metal gate of the PMOS device'20138,361,869'Method for manufacturing suspended fin and gate-all-around field effect transistor'20138,338,084'Patterning method'20128,334,205'Method for removing polymer after etching gate stack structure of high-K gate dielectric/metal gate'20128,324,061'Method for manufacturing semiconductor device'20128,298,927'Method of adjusting metal gate work function of NMOS device'20128,278,026'Method for improving electron-beam'20128,258,063'Method for manufacturing a metal gate electrode/high K dielectric gate stack'20128,163,620'Method for etching Mo-based metal gate stack with aluminium nitride barrier'20127,960,235'Method for manufacturing a MOSFET with a surrounding gate of bulk Si'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2018Based in Beijing, CN· patent location history
2012–2018Patents assigned to INST OF MICROELECTRONICS CAS (37)· patent assignee history
2012–2018Patents assigned to XU QIUXIA (36)· patent assignee history
2012–2018Patents assigned to YIN HUAXIANG (16)· patent assignee history
2012–2017Patents assigned to CHEN DAPENG (14)· patent assignee history
2012–2015Patents assigned to XU GAOBO (10)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INST OF MICROELECTRONICS CAS | 37 | 2012–2018 |
| XU QIUXIAself | 36 | 2012–2018 |
| YIN HUAXIANG | 16 | 2012–2018 |
| CHEN DAPENG | 14 | 2012–2017 |
| XU GAOBO | 10 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beijing, CN | 46 | 2011–2018 |