Inventor
Sung-Woo Han
Inventor
Gyeonggi-do, KR
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores33%
H03KPulse technique22%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses11%
H01LSemiconductor devices6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
G06FElectric digital data processing5%
H10BElectronic memory devices5%
H04LTransmission of digital information, e.g. telegraphic communication2%
H04WWireless communication networks2%
G05FSystems for regulating electric or magnetic variables1%
PatentTitleYear
9,609,742'Electrical characteristics of package substrates and semiconductor packages including the same'20179,595,498'Semiconductor memory device having pads'20179,276,500'Reservoir capacitor and semiconductor device including the same'20169,209,145'Semiconductor memory device having pads'20159,190,372'Semiconductor memory device having pads'20159,124,252'Method for reducing output data noise of semiconductor apparatus and semiconductor apparatus implementing the same'20158,941,406'Method for reducing output data noise of semiconductor apparatus and semiconductor apparatus implementing the same'20158,916,975'Semiconductor memory device having pads'20148,461,878'Input buffer circuit of semiconductor apparatus'20138,373,456'Domain crossing circuit of a semiconductor memory apparatus'20138,339,159'Input buffer circuit of semiconductor apparatus'20128,283,804'Semiconductor IC device having power-sharing and method of power-sharing thereof'20128,278,981'Low power variable delay circuit'20128,189,400'Data alignment circuit of semiconductor memory apparatus'20128,144,530'Semiconductor memory device and method for generating output enable signal'20128,144,531'Latency control circuit, semiconductor memory device including the same, and method for controlling latency'20128,143,940'Internal supply voltage generating circuit and method for generating internal supply voltage'20128,139,480'Communication method based on transmission control protocol and mobile communication terminal to perform the method'20128,120,416'Semiconductor integrated circuit'20128,099,620'Domain crossing circuit of a semiconductor memory apparatus'20128,076,964'Sampling circuit'20118,035,431'Delay locked loop and delay locking method having burst tracking scheme'20118,026,701'Voltage regulator for a synchronous clock system to reduce clock tree jitter'20118,023,356'Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same'20117,969,214'DLL circuit, update control apparatus in DLL circuit and update method of DLL circuit'20117,952,364'Power noise detecting device and power noise control device using the same'20117,936,620'Receiver of semiconductor memory apparatus'20117,915,939'Duty cycle correction apparatus and semiconductor integrated circuit having the same'20117,884,659'Phase mixer and delay locked loop including the same'20117,868,667'Output driving device'20117,863,957'Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same'20117,852,132'Semiconductor integrated circuit'20107,847,592'Buffer circuit of semiconductor memory apparatus'20107,826,306'Semiconductor memory apparatus'20107,821,311'Delay locked loop circuit and memory device having the same'20107,800,416'Data output buffer circuit'20107,786,783'Duty cycle correction circuit with reduced current consumption'20107,755,410'Semiconductor integrated circuit capable of overcoming clock signal jitter'20107,352,719'Method and mobile communication terminal for communicating voice message using packet-switched scheme'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2012Based in Seoul, KR· patent location history
2010–2014Patents assigned to HYNIX SEMICONDUCTOR INC (26)· patent assignee history
2010–2017Based in Gyeonggi-do, KR· patent location history
2010–2012Based in Ichon-shi, KR· patent location history
2011–2012Patents assigned to HAN SUNG-WOO (8)· patent assignee history
2011–2012Patents assigned to KIM YONG-JU (8)· patent assignee history
2011–2012Patents assigned to CHOI HAE-RANG (7)· patent assignee history
2011–2012Based in Ichon-si, KR· patent location history
2012–2017Patents assigned to SK HYNIX INC (9)· patent assignee history
2015–2017Based in Icheon-si, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HYNIX SEMICONDUCTOR INC | 26 | 2010–2014 |
| SK HYNIX INC | 9 | 2012–2017 |
| HAN SUNG-WOOself | 8 | 2011–2012 |
| KIM YONG-JU | 8 | 2011–2012 |
| CHOI HAE-RANG | 7 | 2011–2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Gyeonggi-do, KR | 21 | 2010–2017 |
| Ichon-shi, KR | 11 | 2010–2012 |
| Icheon-si, KR | 3 | 2015–2017 |
| Seoul, KR | 2 | 2008–2012 |
| Ichon-si, KR | 2 | 2011–2012 |