LexDanaLexDanabeta
Inventor

Chong H. Lee

Inventor
San Ramon, CA, US

Overview

97→
Patents
1984–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 97 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication24%
H03KPulse technique21%
G06FElectric digital data processing16%
H03MCoding12%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses6%
H04JMultiplex communication5%
G11CStatic stores3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
H04BTransmission2%
H04WWireless communication networks1%
PatentTitleYear
10,753,302Method of analyzing fuel component using an RF sensor for a vehicle202010,321,426Apparatus and method for detecting synchronization and signals using block data processing201910,216,219Multi-protocol configurable transceiver including configurable deskew in an integrated circuit201910,009,198Configurable multi-lane scrambler for flexible protocol support20189,778,849'Method of operating data storage device using size and write speed information and method of operating system including the same'20179,531,646'Multi-protocol configurable transceiver including configurable deskew in an integrated circuit'20169,438,272'Digital phase locked loop circuitry and methods'20169,367,509'Configurable multi-lane scrambler for flexible protocol support'20169,270,500'Apparatus and methods of dynamic transmit equalization'20169,170,952'Configurable multi-standard device interface'20159,077,330'Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits'20159,049,120'Method and system for operating a communication circuit during a low-power state'20158,989,284'Method and system for transitioning a communication circuit to a low-power state'20158,984,380'Method and system for operating a communication circuit configurable to support one or more data rates'20158,949,493'Configurable multi-lane scrambler for flexible protocol support'20158,838,766'Module and method for semantic negotiation'20148,804,890'Digital phase locked loop circuitry and methods'20148,787,352'Heterogeneous transceiver architecture for wide range programmability of programmable logic devices'20148,788,862'Method and system for efficiently transitioning a communication circuit from a low-power state'20148,732,375'Multi-protocol configurable transceiver with independent channel-based PCS in an integrated circuit'20148,630,198'Apparatus and methods of dynamic transmit equalization'20148,570,197'Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits'20138,477,831'Multi-protocol multiple-data-rate auto-speed negotiation architecture for a device'20138,462,908'Digital phase locked loop circuitry and methods'20138,458,383'Flexible interface for stacked protocol in a programmable integrated circuit device'20138,363,770'Oversampling with programmable pointer adjustment'20138,291,255'CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device'20128,165,191'Multi-protocol channel-aggregated configurable transceiver in an integrated circuit'20128,098,087'Method and apparatus for standby voltage offset cancellation'20127,984,209'Data interface methods and circuitry with reduced latency'20117,940,814'Heterogeneous transceiver architecture for wide range programmability of programmable logic devices'20117,925,913'CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device'20117,869,553'Digital phase locked loop circuitry and methods'20117,869,343'Field programmable gate array architectures and methods for supporting forward error correction'20117,848,318'Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits'20107,728,763'High resolution ranging apparatus and method using UWB'20107,724,598'Megafunction block and interface'20107,698,482'Multiple data rates in integrated circuit device serial interface'20107,684,532'Clock data recovery circuitry associated with programmable logic device circuitry'20107,684,477'Multi-protocol low latency automatic speed negotiation architecture for an embedded high speed serial interface in a programmable logic device'20107,675,326'Dynamically-adjustable differential output drivers'20107,659,838'Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits'20107,656,187'Multi-channel communication circuitry for programmable logic device integrated circuits and the like'20107,646,217'Programmable logic device with serial interconnect'20107,627,806'Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device'20097,616,657'Heterogeneous transceiver architecture for wide range programmability of programmable logic devices'20097,577,166'Programmable logic devices with multi-standard byte synchronization and channel alignment for communication'20097,558,309'Low-interference UWB wireless communication system and processing method thereof and storage medium recorded program of the same'20097,538,578'Multiple data rates in programmable logic device serial interface'20097,525,340'Programmable logic device architecture for accommodating specialized circuitry'20097,436,210'Next generation 8B10B architecture'20087,397,270'Dynamically-adjustable differential output drivers'20087,386,767'Programmable bit error rate monitor for serial interface'20087,386,347'Electric stimilator for alpha-wave derivation'20087,366,267'Clock data recovery with double edge clocking based phase detector and serializer/deserializer'20087,362,833'Dynamic special character selection for use in byte alignment circuitry'20087,343,569'Apparatus and method for reset distribution'20087,333,570'Clock data recovery circuitry associated with programmable logic device circuitry'20087,310,399'Clock signal circuitry for multi-protocol high-speed serial interface circuitry'20077,305,058'Multi-standard clock rate matching circuitry'20077,292,070'Programmable PPM detector'20077,272,677'Multi-channel synchronization for programmable logic device serial interface'20077,268,582'DPRIO for embedded hard IP'20077,259,699'Circuitry for providing configurable running disparity enforcement in 8B/10B encoding and error detection'20077,227,918'Clock data recovery circuitry associated with programmable logic device circuitry'20077,199,732'Data converter with reduced component count for padded-protocol interface'20077,183,797'Next generation 8B10B architecture'20077,180,972'Clock signal circuitry for multi-protocol high-speed serial interface circuitry'20077,162,553'Correlating high-speed serial interface data and FIFO status signals in programmable logic devices'20077,151,470'Data converter with multiple conversions for padded-protocol interface'20067,151,397'Voltage controlled oscillator programmable delay cells'20067,138,837'Digital phase locked loop circuitry and methods'20067,131,024'Multiple transmit data rates in programmable logic device serial interface'20067,095,340'Run-length violation detection circuitry and methods for using the same'20067,088,133'Programmable logic device with high speed serial interface circuitry'20067,071,726'Selectable dynamic reconfiguration of programmable embedded IP'20067,064,685'Data converter with reduced component count for padded-protocol interface'20067,046,174'Byte alignment for serial data receiver'20067,039,787'Byte alignment circuitry'20067,028,270'Apparatus and method for reset distribution'20067,002,368'Programmable logic device with high speed serial interface circuitry'20066,985,021'Circuits and techniques for conditioning differential signals'20066,970,117'Byte alignment for serial data receiver'20056,963,223'Programmable logic devices with multi-standard byte synchronization and channel alignment for communication'20056,943,588'Dynamically-adjustable differential output drivers'20056,911,841'Programmable logic device with high speed serial interface circuitry'20056,888,480'Run-length violation detection circuitry and methods for using the same'20056,888,376'Multiple data rates in programmable logic device serial interface'20056,867,616'Programmable logic device serial interface having dual-use phase-locked loop circuitry'20056,854,044'Byte alignment circuitry'20056,842,034'Selectable dynamic reconfiguration of programmable embedded IP'20056,771,105'Voltage controlled oscillator programmable delay cells'20046,750,675'Programmable logic devices with multi-standard byte synchronization and channel alignment for communication'20046,724,328'Byte alignment for serial data receiver'20046,650,140'Programmable logic device with high speed serial interface circuitry'2003D0338104'Carrying case for a computer'19934,434,894'Dual purpose pallet sheet'1984

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1984–1993Based in Lake Forest, IL, US· patent location history
1993–2016Patents assigned to LEE CHONG H (17)· patent assignee history
2003–2019Patents assigned to ALTERA CORP (88)· patent assignee history
2003–2019Based in San Ramon, CA, US· patent location history
2007Based in San Bernardino, CA, US· patent location history
2008–2017Based in Seoul, KR· patent location history
2012–2016Patents assigned to VIJAYARAGHAVAN DIVYA (11)· patent assignee history
2012–2016Patents assigned to WORTMAN CURT (4)· patent assignee history
2014–2019Patents assigned to SAMSUNG ELECTRONICS CO LTD (3)· patent assignee history
2019–2020Based in Jeju-si, KR· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ALTERA CORP882003–2019
LEE CHONG Hself171993–2016
VIJAYARAGHAVAN DIVYA112012–2016
WORTMAN CURT42012–2016
SAMSUNG ELECTRONICS CO LTD32014–2019
Locations
LocationPatentsSpan
San Ramon, California, US872003–2019
Seoul, KR52008–2017
Jeju-si, KR22019–2020
Lake Forest, Illinois, US21984–1993
San Bernardino, California, US12007