LexDanaLexDanabeta
Inventor

Min-hwa Chi

Inventor
Malta, NY, US

Overview

256→
Patents
1995–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 256 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices31%
H01LSemiconductor devices20%
H10BElectronic memory devices12%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
G11CStatic stores8%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
H03KPulse technique1%
H10NElectric solid-state devices not otherwise provided for1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
11,011,604Semiconductor device with recessed source/drain contacts and a gate contact positioned above the active region202110,756,213FinFET with multilayer fins for multi-value logic (MVL) applications202010,622,463Method, apparatus and system for improved performance using tall fins in finFET devices202010,572,380Structures of bottom select transistor for embedding 3D-NAND in BEOL and methods202010,483,283Flash memory device and manufacture thereof201910,475,899Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby201910,438,955Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods201910,396,155Semiconductor device with recessed source/drain contacts and a gate contact positioned above the active region201910,388,790FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming201910,347,740Fin structures and multi-Vt scheme based on tapered fin and method to form201910,332,834Semiconductor fuses with nanowire fuse links and fabrication methods thereof201910,297,609Flash memory device and manufacture thereof201910,290,654Circuit structures with vertically spaced transistors and fabrication methods201910,290,634Multiple threshold voltages using fin pitch and profile201910,276,390Method and apparatus for reducing threshold voltage mismatch in an integrated circuit201910,269,811Selective SAC capping on fin field effect transistor structures and related methods201910,243,059Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins201910,204,991Transistor structures and fabrication methods thereof201910,177,157Transistor structure having multiple n-type and/or p-type elongated regions intersecting under common gate201910,170,353Devices and methods for dynamically tunable biasing to backplates and wells201910,170,377Memory cell with recessed source/drain contacts to reduce capacitance201910,170,315Semiconductor device having local buried oxide201910,164,041Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby201810,147,496OTPROM for post-process programming using selective breakdown201810,147,802FINFET circuit structures with vertically spaced transistors and fabrication methods201810,128,333FinFET with isolated source and drain201810,121,893Integrated circuit structure without gate contact and method of forming same201810,115,807Method, apparatus and system for improved performance using tall fins in finFET devices201810,115,738Self-aligned back-plane and well contacts for fully depleted silicon on insulator device201810,096,604Selective SAC capping on fin field effect transistor structures and related methods201810,068,766Oxidizing and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines201810,056,331Programmable via devices with metal/semiconductor via links and fabrication methods thereof201810,056,468Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins201810,038,096Three-dimensional finFET transistor with portion(s) of the fin channel removed in gate-last flow201810,032,910FinFET devices having asymmetrical epitaxially-grown source and drain regions and methods of forming the same201810,014,303Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods201810,003,302Modified tunneling field effect transistors and fabrication methods20189,984,932Semiconductor fin loop for use with diffusion break20189,964,605Methods for crossed-fins FinFET device for sensing and measuring magnetic fields20189,916,903'OTPROM for post-process programming using selective breakdown'20189,905,673'Stress memorization and defect suppression techniques for NMOS transistor devices'20189,881,738'Capacitor structures with embedded electrodes and fabrication methods thereof'20189,865,603'Transistor structure having N-type and P-type elongated regions intersecting under common gate'20189,842,927'Integrated circuit structure without gate contact and method of forming same'20179,831,248Embedded DRAM cells having capacitors within trench silicide trenches of a semiconductor structure20179,831,346FinFETs with air-gap spacers and methods for forming the same20179,831,175Method, apparatus, and system for E-fuse in advanced CMOS technologies20179,824,748'SRAM bitcell structures facilitating biasing of pull-up transistors'20179,818,689'Metal-insulator-metal capacitor and methods of fabrication'20179,812,393'Programmable via devices with metal/semiconductor via links and fabrication methods thereof'20179,805,982'Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETs'20179,799,661'SRAM bitcell structures facilitating biasing of pull-down transistors'20179,799,514'Protecting, oxidizing, and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines'20179,768,325'Diodes and fabrication methods thereof'20179,761,691'Integrated circuits including replacement gate structures and methods for fabricating the same'20179,754,903'Semiconductor structure with anti-efuse device'20179,741,615'Contacts for a fin-type field-effect transistor'20179,735,057'Fabricating field effect transistor(s) with stressed channel region(s) and low-resistance source/drain regions'20179,734,897'SRAM bitcell structures facilitating biasing of pass gate transistors'20179,716,138'Devices and methods for dynamically tunable biasing to backplates and wells'20179,711,619'Stress memorization and defect suppression techniques for NMOS transistor devices'20179,704,759'Methods of forming CMOS based integrated circuit products using disposable spacers'20179,698,241'Integrated circuits with replacement metal gates and methods for fabricating the same'20179,698,269'Conformal nitridation of one or more fin-type transistor layers'20179,691,497'Programmable devices with current-facilitated migration and fabrication methods'20179,673,757'Modified tunneling field effect transistors and fabrication methods'20179,659,862'Method, apparatus, and system for e-fuse in advanced CMOS technologies'20179,653,583'Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices'20179,647,073'Transistor structures and fabrication methods thereof'20179,640,538'Embedded DRAM in replacement metal gate technology'20179,620,425'Method of adjusting spacer thickness to provide variable threshold voltages in FinFETs'20179,601,495'Three-dimensional semiconductor device with co-fabricated adjacent capacitor'20179,601,428'Semiconductor fuses with nanowire fuse links and fabrication methods thereof'20179,583,625'Fin structures and multi-Vt scheme based on tapered fin and method to form'20179,583,479'Semiconductor charge pump with imbedded capacitor'20179,577,063'Bipolar transistor, band-gap reference circuit and virtual ground reference circuit and methods of fabricating thereof'20179,570,572'Multiple layer interface formation for semiconductor structure'20179,564,447'Methods for fabricating programmable devices and related structures'20179,559,166'Fabricating transistors having resurfaced source/drain regions with stressed portions'20179,548,318'Connecting to back-plate contacts or diode junctions through a RMG electrode and resulting devices'20179,548,357'Shallow trench isolation structure with sigma cavity'20179,543,298'Single diffusion break structure and cuts later method of making'20179,536,991'Single diffusion break structure'20179,524,911'Method for creating self-aligned SDB for minimum gate-junction pitch and epitaxy formation in a fin-type IC device'20169,508,795'Methods of fabricating nanowire structures'20169,502,301'Fabrication methods for multi-layer semiconductor structures'20169,490,174'Fabricating raised fins using ancillary fin structures'20169,478,625'Metal resistor using FinFET-based replacement gate process'20169,460,996'Integrated device with inductive and capacitive portions and fabrication methods'20169,443,771'Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology'20169,425,100'Methods of facilitating fabricating transistors'20169,418,899'Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology'20169,419,015'Method for integrating thin-film transistors on an isolation region in an integrated circuit and resulting device'20169,396,995'MOL contact metallization scheme for improved yield and device reliability'20169,385,126'Silicon-on-insulator finFET with bulk source and drain'20169,385,124'Methods of forming reduced thickness spacers in CMOS based integrated circuit products'20169,379,209'Selectively forming a protective conductive cap on a metal gate electrode'20169,379,186'Fet structure for minimum size length/width devices for performance boost and mismatch reduction'20169,362,277'FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming'20169,337,340'FinFET with active region shaped structures and channel separation'20169,337,324'Bipolar transistor, band-gap reference circuit and virtual ground reference circuit'20169,331,159'Fabricating transistor(s) with raised active regions having angled upper surfaces'20169,312,145'Conformal nitridation of one or more fin-type transistor layers'20169,299,608'T-shaped contacts for semiconductor device'20169,263,587'Fin device with blocking layer in channel region'20169,252,272'FinFET semiconductor device having local buried oxide'20169,209,079'Conductor layout technique to reduce stress-induced void formations'20159,153,496'Methods of manufacturing integrated circuits having FinFET structures with epitaxially formed source/drain regions'20159,142,316'Embedded selector-less one-time programmable non-volatile memory'20159,142,673'Devices and methods of forming bulk FinFETS with lateral seg for source and drain on dielectrics'20159,087,743'Silicon-on-insulator finFET with bulk source and drain'20159,076,791'MOS transistor operated as OTP cell with gate dielectric operating as an e-fuse element'20159,076,868'Shallow trench isolation structure with sigma cavity'20159,064,888'Forming tunneling field-effect transistor with stacking fault and resulting device'20159,023,705'Methods of forming stressed multilayer FinFET devices with alternative channel materials'20159,012,986'Combination FinFET and planar FET semiconductor device and methods of making such a device'20159,012,286'Methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices'20159,007,803'Integrated circuits with programmable electrical connections and methods for fabricating the same'20159,006,066'FinFET with active region shaped structures and channel separation'20158,975,091'Method of fabricating a magnetic tunnel junction device'20158,946,029'Methods of manufacturing integrated circuits having FinFET structures with epitaxially formed source/drain regions'20158,906,768'Wrap around stressor formation'20148,836,141'Conductor layout technique to reduce stress-induced void formations'20148,815,659'Methods of forming a FinFET semiconductor device by performing an epitaxial growth process'20148,772,117'Combination FinFET and planar FET semiconductor device and methods of making such a device'20148,772,102'Methods of forming self-aligned contacts for a semiconductor device formed using replacement gate techniques'20148,741,723'Methods of forming self-aligned contacts for a semiconductor device'20148,685,812'Logic switch and circuits utilizing the switch'20148,674,413'Methods of forming fins and isolation regions on a FinFET semiconductor device'20148,617,996'Fin removal method'20138,574,927'Magnetic tunnel junction device and its fabricating method'20138,466,505'Multi-level flash memory cell capable of fast programming'20138,451,646'Resistive random access memory and the method of operating the same'20138,435,802'Conductor layout technique to reduce stress-induced void formations'20138,421,166'Semiconductor device and fabrication thereof'20138,362,528'Logic switch and circuits utilizing the switch'20138,273,639'Atomic layer deposition method and semiconductor device formed by the same'20128,264,863'Green transistor for nano-Si ferro-electric RAM and method of operating the same'20128,208,286'Green transistor for resistive random access memory and method of operating the same'20128,158,512'Atomic layer deposition method and semiconductor device formed by the same'20127,994,040'Semiconductor device and fabrication thereof'20117,804,155'Vertical resistors'20107,737,532'Hybrid Schottky source-drain CMOS for high mobility and low barrier'20107,709,386'Atomic layer deposition method and semiconductor device formed by the same'20107,635,882'Logic switch and circuits utilizing the switch'20097,633,110'Memory cell'20097,589,387'SONOS type two-bit FinFET flash memory cell'20097,564,105'Quasi-plannar and FinFET-like transistors on bulk silicon'20097,498,657'Vertical resistors and band-gap voltage reference circuits'20097,371,634'Amorphous carbon contact film for contact hole etch process'20087,320,926'Shallow trench filled with two or more dielectrics for isolation and coupling for stress control'20087,291,553'Method for forming dual damascene with improved etch profiles'20077,176,537'High performance CMOS with metal-gate and Schottky source/drain'20077,129,140'Method of forming polysilicon gate structures with specific edge profiles for optimization of LDD offset spacing'20067,106,088'Method of predicting high-k semiconductor device lifetime'20067,081,395'Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials'20067,078,766'Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents'20067,018,886'Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control'20067,002,213'Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents'20066,949,471'Method for fabricating poly patterns'20056,943,391'Modification of carrier mobility in a semiconductor device'20056,905,929'Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process'20056,885,068'Storage element and SRAM cell structures using vertical FETs controlled by adjacent junction bias through shallow trench isolation'20056,855,587'Gate-controlled, negative resistance diode device using band-to-band tunneling'20056,828,211'Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control'20046,822,283'Low temperature MIM capacitor for mixed-signal/RF applications'20046,759,699'Storage element and SRAM cell structures using vertical FETS controlled by adjacent junction bias through shallow trench isolation'20046,670,279'Method of forming shallow trench isolation with rounded corners and divot-free by using in-situ formed spacers'20036,657,240'Gate-controlled, negative resistance diode device using band-to-band tunneling'20036,579,791'Method to form dual damascene structure'20036,555,442'Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer'20036,552,397'Charge pump device formed on silicon-on-insulator and operation method'20036,528,366'Fabrication methods of vertical metal-insulator-metal (MIM) capacitor for advanced embedded DRAM applications'20036,509,606'Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process'20036,501,120'Capacitor under bitline (CUB) memory cell structure employing air gap void isolation'20026,501,109'Active CMOS pixel with exponential output based on the GIDL mechanism'20026,500,706'Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM'20026,486,025'Methods for forming memory cell structures'20026,486,529'Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications'20026,373,090'Scheme of capacitor and bit-line at same level and its fabrication method for 8F2 DRAM cell with minimum bit-line coupling noise'20026,362,012'Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications'20026,288,943'Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate'20016,281,550'Transistor and logic circuit of thin silicon-on-insulator wafers based on gate induced drain leakage currents'20016,271,084'Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process'20016,262,447'Single polysilicon DRAM cell and array with current gain'20016,255,713'Current source using merged vertical bipolar transistor based on gate induced gate leakage current'20016,240,015'Method for reading 2-bit ETOX cells using gate induced drain leakage current'20016,200,852'Method to fabricate DRAM capacitor'20016,184,548'DRAM cell and array to store two-bit data having merged stack capacitor and trench capacitor'20016,181,601'Flash memory cell using p+/N-well diode with double poly floating gate'20016,175,605'Edge triggered delay line, a multiple adjustable delay line circuit, and an application of same'20016,174,770'Method for forming a crown capacitor having HSG for DRAM memory'20016,174,767'Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise'20016,171,923'Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor'20016,163,482'One transistor EEPROM cell using ferro-electric spacer'20006,160,286'Method for operation of a flash memory using n+/p-well diode'20006,144,075'CMOS inverter using gate induced drain leakage current'20006,143,607'Method for forming flash memory of ETOX-cell programmed by band-to-band tunneling induced substrate hot electron and read by gate induced drain leakage current'20006,136,635'Method for forming a bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region'20006,133,780'Digitally tunable voltage reference using a neuron MOSFET'20006,133,604'NOR array architecture and operation methods for ETOX cells capable of full EEPROM functions'20006,111,925'Clock synchronized delay scheme using edge-triggered delay lines and latches with one clock lock time'20006,111,286'Low voltage low power n-channel flash memory cell using gate induced drain leakage current'20006,111,788'Method for programming and erasing a triple-poly split-gate flash'20006,091,635'Electron injection method for substrate-hot-electron program and erase V.sub.T tightening for ETOX cell'20006,087,690'Single polysilicon DRAM cell with current gain'20006,088,058'Capacitive coupled bipolar active pixel imager having overflow protection and electronic shutter'20006,088,259'SRAM cell using two single transistor inverters'20006,084,262'Etox cell programmed by band-to-band tunneling induced substrate hot electron and read by gate induced drain leakage current'20006,080,601'Method for forming a bipolar-based active pixel sensor cell with metal contact and increased capacitive coupling to the base region'20006,064,053'Operation methods for active BiCMOS pixel for electronic shutter and image-lag elimination'20006,060,742'ETOX cell having bipolar electron injection for substrate-hot-electron program'20006,025,625'Single-poly EEPROM cell structure operations and array architecture'20006,018,177'DRAM cell and array to store two-bit data'20006,016,279'DRAM sensing scheme and isolation circuit'20006,011,295'Neural network active pixel cell'20006,008,508'ESD Input protection using a floating gate neuron MOSFET as a tunable trigger element'19995,998,820'Fabrication method and structure for a DRAM cell with bipolar charge amplification'19995,981,335'Method of making stacked gate memory cell structure'19995,976,945'Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor'19995,962,844'Active pixel image cell with embedded memory and pixel level signal processing capability'19995,945,722'Color active pixel sensor cell with oxide color filter'19995,940,324'Single-poly EEPROM cell that is programmable and erasable in a low-voltage environment'19995,936,898'Bit-line voltage limiting isolation circuit'19995,932,873'Capacitor-coupled bipolar active pixel sensor with integrated electronic shutter'19995,920,785'Dram cell and array to store two-bit data having merged stack capacitor and trench capacitor'19995,917,748'Multi-level DRAM sensing scheme'19995,909,619'Method for forming a DRAM cell and array to store two-bit data'19995,908,311'Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells'19995,889,700'High density EEPROM array using self-aligned control gate and floating gate for both access transistor and memory cell and method of operating same'19995,872,032'Fabrication method for a DRAM cell with bipolar charge amplification'19995,870,343'DRAM sensing scheme for eliminating bit-line coupling noise'19995,856,222'Method of fabricating a high density EEPROM cell'19995,854,100'Method of forming a new bipolar/CMOS pixel for high resolution imagers'19985,847,422'MOS-based active pixel sensor cell that utilizes the parasitic bipolar action of the cell to output image data'19985,837,574'Method of manufacturing a thin poly, capacitor coupled contactless imager with high resolution and wide dynamic range'19985,814,856'Variable and tunable V.sub.T MOSFET with poly and/or buried diffusion'19985,808,937'Self-convergent method for programming FLASH and EEPROM memory cells that moves the threshold voltage from an erased threshold voltage range to one of a plurality of programmed threshold voltage ranges'19985,806,054'Neuron MOSFET module structure for binary logic circuits'19985,786,623'Bipolar-based active pixel sensor cell with metal contact and increased capacitive coupling to the base region'19985,776,795'Method of making a contactless capacitor-coupled bipolar active pixel sensor with intergrated electronic shutter'19985,760,458'Bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region'19985,761,126'Single-poly EPROM cell that utilizes a reduced programming voltage to program the cell'19985,753,954'Single-poly neuron MOS transistor'19985,734,191'Contactless capacitor-coupled bipolar active pixel sensor with integrated electronic shutter'19985,710,446'Active pixel sensor cell that utilizes a parasitic transistor to reset the photodiode of the cell'19985,608,243'Single split-gate MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range'19975,594,685'Method for programming a single EPROM or flash memory cell to store multiple bits of data that utilizes a punchthrough current'19975,587,949'Method for programming an ETOX EPROM or flash memory when cells of the array are formed to store multiple bits of data'19965,587,596'Single MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range'19965,576,237'Method of manufacturing a capacitor coupled contactless imager with high resolution and wide dynamic range'19965,566,044'Base capacitor coupled photosensor with emitter tunnel oxide for very wide dynamic range in a contactless imaging array'19965,557,567'Method for programming an AMG EPROM or flash memory when cells of the array are formed to store multiple bits of data'19965,552,619'Capacitor coupled contactless imager with high resolution and wide dynamic range'19965,511,021'Method for programming a single EPROM or flash memory cell to store multiple levels of data that utilizes a forward-biased source-to-substrate junction'19965,477,485'Method for programming a single EPROM or FLASH memory cell to store multiple levels of data that utilizes a floating substrate'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2005Patents assigned to NAT SEMICONDUCTOR CORP (27)· patent assignee history
1995–2009Based in Palo Alto, CA, US· patent location history
1998–2002Patents assigned to VANGUARD INT SEMICONDUCT CORP (19)· patent assignee history
1998–2015Based in Hsinchu, TW· patent location history
2001–2014Patents assigned to TAIWAN SEMICONDUCTOR MFG (43)· patent assignee history
2010–2020Based in Shanghai, CN· patent location history
2012–2015Patents assigned to CHI MIN-HWA (13)· patent assignee history
2013–2020Patents assigned to GLOBALFOUNDRIES INC (120)· patent assignee history
2013–2021Based in Malta, NY, US· patent location history
2017–2020Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
GLOBALFOUNDRIES INC1202013–2020
TAIWAN SEMICONDUCTOR MFG432001–2014
NAT SEMICONDUCTOR CORP271995–2005
VANGUARD INT SEMICONDUCT CORP191998–2002
CHI MIN-HWAself132012–2015
Locations
LocationPatentsSpan
Malta, New York, US772013–2021
Hsinchu, TW721998–2015
San Jose, California, US432017–2020
Palo Alto, California, US401995–2009
Shanghai, CN112010–2020