Inventor
Hartmut Ruelke
Inventor
Dresden, DE
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1035%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%
C23CCoating metallic material12%
H10DInorganic electric semiconductor devices12%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H01LSemiconductor devices2%
H05HPlasma technique2%
PatentTitleYear
8,847,205'Spacer for a gate electrode having tensile stress and a method of forming the same'20148,772,178'Technique for forming a dielectric interlayer above a structure including closely spaced lines'20148,759,232'Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress'20148,741,787'Increased density of low-K dielectric materials in semiconductor devices by applying a UV treatment'20148,609,555'Increased stability of a complex material stack in a semiconductor device by providing fluorine enriched interfaces'20138,450,172'Non-insulating stressed material layers in a contact level of semiconductor devices'20138,415,257'Enhanced adhesion of PECVD carbon on dielectric materials by providing an adhesion interface'20138,338,284'Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer'20128,211,795'Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment'20128,084,088'Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers'20117,998,882'Particle reduction in PECVD processes for depositing low-k material by using a plasma assisted post-deposition step'20117,807,233'Method of forming a TEOS cap layer at low temperature and reduced deposition rate'20107,381,602'Method of forming a field effect transistor comprising a stressed channel region'20087,381,660'Dielectric barrier layer for a copper metallization layer having a varying silicon concentration along its thickness'20087,341,903'Method of forming a field effect transistor having a stressed channel region'20087,326,646'Nitrogen-free ARC layer and a method of manufacturing the same'20087,314,824'Nitrogen-free ARC/capping layer and method of manufacturing the same'20087,030,044'Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric'20067,022,602'Nitrogen-enriched low-k barrier layer for a copper metallization layer'20066,989,601'Copper damascene with low-k capping layer and improved electromigration reliability'20066,927,161'Low-k dielectric layer stack including an etch indicator layer for use in the dual damascene technique'20056,893,956'Barrier layer for a copper metallization layer including a low-k dielectric'20056,797,652'Copper damascene with low-k capping layer and improved electromigration reliability'20046,720,242'Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer'20046,599,827'Methods of forming capped copper interconnects with improved electromigration resistance'20036,596,631'Method of forming copper interconnect capping layers with improved interface and adhesion'20036,569,768'Surface treatment and capping layer process for producing a copper interface in a semiconductor device'20036,506,677'Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance'20036,372,668'Method of forming silicon oxynitride films'20026,368,948'Method of forming capped copper interconnects with reduced hillocks'20026,235,654'Process for forming PECVD nitride with a very low deposition rate'20016,221,793'Process for forming PECVD undoped oxide with a super low deposition rate on a single state deposition'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2012Patents assigned to ADVANCED MICRO DEVICES INC (21)· patent assignee history
2001–2006Based in Wilschdorf, DE· patent location history
2002–2014Based in Dresden, DE· patent location history
2010–2014Patents assigned to GLOBALFOUNDRIES INC (11)· patent assignee history
2011–2014Patents assigned to RUELKE HARTMUT (9)· patent assignee history
2012–2014Patents assigned to HOHAGE JOERG (4)· patent assignee history
2013–2014Patents assigned to STRECK CHRISTOF (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 21 | 2001–2012 |
| GLOBALFOUNDRIES INC | 11 | 2010–2014 |
| RUELKE HARTMUTself | 9 | 2011–2014 |
| HOHAGE JOERG | 4 | 2012–2014 |
| STRECK CHRISTOF | 3 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dresden, DE | 26 | 2002–2014 |
| Wilschdorf, DE | 6 | 2001–2006 |