LexDanaLexDanabeta
Inventor

Takashi Orimoto

Inventor
Sunnyvale, CA, US

Overview

62→
Patents
1986–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 62 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices32%
H10DInorganic electric semiconductor devices19%
H01LSemiconductor devices6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
G11CStatic stores4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
B29DProducing particular articles from plastics or from substances in a plastic state3%
B29LIndexing scheme associated with subclass b29c, relating to particular articles3%
B82YSpecific uses or applications of nanostructures3%
PatentTitleYear
10,768,362Arrays of integrated analytical devices and methods for production202010,403,639Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same201910,310,178Arrays of integrated analytical devices and methods for production201910,297,610Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same201910,103,169Method of making a three-dimensional memory device using a multi-step hot phosphoric acid wet etch process20189,946,017Arrays of integrated analytical devices and methods for production20189,754,836'Packaging methods for fabrication of analytical device packages and analytical device packages made thereof'20179,658,161'Arrays of integrated analytical devices and methods for production'20179,379,120'Metal control gate structures and air gap isolation in non-volatile memory'20169,372,308'Arrays of integrated analytical devices and methods for production'20168,946,803'Method of forming a floating gate with a wide base and a narrow stem'20158,946,022'Integrated nanostructure-based non-volatile memory fabrication'20158,877,586'Process for forming resistive switching memory cells using nano-particles'20148,803,220'P-type control gate in non-volatile storage'20148,587,049'Memory cell system with charge trap'20138,546,214'P-type control gate in non-volatile storage and methods for forming same'20138,546,152'Enhanced endpoint detection in non-volatile memory fabrication processes'20138,492,224'Metal control gate structures and air gap isolation in non-volatile memory'20138,409,951'Metal control gate formation in non-volatile storage'20138,383,479'Integrated nanostructure-based non-volatile memory fabrication'20138,278,203'Metal control gate formation in non-volatile storage'20128,263,465'Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer'20128,222,091'Damascene method of making a nonvolatile memory device'20128,207,036'Method for forming self-aligned dielectric cap above floating gate'20128,193,055'Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution'20128,143,156'Methods of forming high density semiconductor devices using recursive spacer technique'20128,143,661'Memory cell system with charge trap'20128,105,867'Self-aligned three-dimensional non-volatile memory fabrication'20128,097,498'Damascene method of making a nonvolatile memory device'20128,030,160'Methods of forming NAND flash memory with fixed charge'20117,960,266'Spacer patterns using assist layer for high density semiconductor devices'20117,939,407'Composite charge storage structure formation in non-volatile memory using etch stop technologies'20117,919,809'Dielectric layer above floating gate for reducing leakage current'20117,915,664'Non-volatile memory with sidewall channels and raised source/drain regions'20117,915,124'Method of forming dielectric layer above floating gate for reducing leakage current'20117,888,210'Non-volatile memory fabrication and isolation for composite charge storage structures'20117,863,128'Non-volatile memory device with improved erase speed'20117,807,529'Lithographically space-defined charge storage regions in non-volatile memory'20107,795,080'Methods of forming integrated circuit devices using composite spacer structures'20107,773,403'Spacer patterns using assist layer for high density semiconductor devices'20107,736,973'Non-volatile memory arrays having dual control gate cell structures and a thick control gate dielectric and methods of forming'20107,732,275'Methods of forming NAND flash memory with fixed charge'20107,723,186'Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer'20107,704,832'Integrated non-volatile memory and peripheral circuitry fabrication'20107,619,926'NAND flash memory with fixed charge'20097,615,447'Composite charge storage structure formation in non-volatile memory using etch stop technologies'20097,592,223'Methods of fabricating non-volatile memory with integrated select and peripheral circuitry and post-isolation memory cell formation'20097,592,225'Methods of forming spacer patterns using assist layer for high density semiconductor devices'20097,582,529'Methods of fabricating non-volatile memory with integrated peripheral circuitry and pre-isolation memory cell formation'20097,495,282'NAND memory with virtual channel'20097,494,870'Methods of forming NAND memory with virtual channel'20097,446,369'SONOS memory cell having high-K dielectric'20087,444,221'Vehicle backward movement detection apparatus and vehicle braking force control apparatus'20087,414,277'Memory cell having combination raised source and drain and method of fabricating same'20087,354,826'Method for forming memory array bitlines comprising epitaxially grown silicon and related structure'20087,294,547'SONOS memory cell having a graded high-K dielectric'20077,202,128'Method of forming a memory device having improved erase speed'20075,850,231'Electronic device having ferroelectric memory'19985,778,205'Data communication system and portable data processing terminal used therein'19985,701,580'Information providing systems and portable electronic devices'19975,576,650'Reset circuit of electronic device'19964,618,146'Video game apparatus allowing for a variation in playing sequence'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–1998Based in Akiruno, JP· patent location history
2007–2011Based in Mountain View, CA, US· patent location history
2008Based in Susono, JP· patent location history
2009–2011Patents assigned to SANDISK CORP (20)· patent assignee history
2009–2020Based in Sunnyvale, CA, US· patent location history
2011–2016Patents assigned to SANDISK TECHNOLOGIES INC (15)· patent assignee history
2012–2015Patents assigned to PURAYATH VINOD ROBERT (12)· patent assignee history
2012–2015Patents assigned to MATAMIS GEORGE (11)· patent assignee history
2012–2013Patents assigned to ORIMOTO TAKASHI (11)· patent assignee history
2019Based in Yokkaichi, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SANDISK CORP202009–2011
SANDISK TECHNOLOGIES INC152011–2016
PURAYATH VINOD ROBERT122012–2015
MATAMIS GEORGE112012–2015
ORIMOTO TAKASHIself112012–2013
Locations
LocationPatentsSpan
Sunnyvale, California, US482009–2020
Mountain View, California, US62007–2011
Yokkaichi, JP22019
Akiruno, JP21997–1998
Susono, JP12008