Inventor
Chenting Lin
Inventor
Poughkeepsie, NY, US
Overview
Patents· 14 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1029%
H10DInorganic electric semiconductor devices16%
B24BMachines, devices, or processes for grinding or polishing13%
H10BElectronic memory devices13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
B82YSpecific uses or applications of nanostructures3%
C23CCoating metallic material3%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light3%
Y02PClimate change mitigation technologies in the production or processing of goods3%
PatentTitleYear
7,319,270'Multi-layer electrode and method of forming the same'20086,943,113'Metal chemical polishing process for minimizing dishing during semiconductor wafer fabrication'20056,794,705'Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials'20046,685,796'CMP uniformity'20046,459,709'Wavelength-tunable semiconductor laser diode'20026,432,725'Methods for crystallizing metallic oxide dielectric films at low temperature'20026,429,131'CMP uniformity'20026,420,267'Method for forming an integrated barrier/plug for a stacked capacitor'20026,413,866'Method of forming a solute-enriched layer in a substrate surface and article formed thereby'20026,339,007'Capacitor stack structure and method of fabricating description'20026,281,114'Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication'20016,222,220'Extended trench for preventing interaction between components of stacked capacitors'20016,132,294'Method of enhancing semiconductor wafer release'20005,972,787'CMP process using indicator areas to determine endpoint'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2002Patents assigned to IBM (6)· patent assignee history
1999–2008Based in Poughkeepsie, NY, US· patent location history
2000–2001Patents assigned to SIEMENS AG (2)· patent assignee history
2001–2008Patents assigned to INFINEON TECHNOLOGIES AG (8)· patent assignee history
2002Patents assigned to NOVA CRYSTALS INC (1)· patent assignee history
2002Based in Poughkeepsi, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 8 | 2001–2008 |
| IBM | 6 | 1999–2002 |
| SIEMENS AG | 2 | 2000–2001 |
| NOVA CRYSTALS INC | 1 | 2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 13 | 1999–2008 |
| Poughkeepsi, New York, US | 1 | 2002 |