Inventor

Chit Hwei Ng

Inventor

Singapore, SG

Overview

22→

Patents

2002–2011

Patent span

Electricity

Primary field (CPC H)

Patents· 22 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices38%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1030%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%

H01FMagnets4%

H01GCapacitors4%

Y10TTechnical subjects covered by former us classification4%

H01HElectric switches2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

PatentTitleYear

8,021,954'Integrated circuit system with hierarchical capacitor and method of manufacture thereof'2011 7,323,736'Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits'2008 7,250,669'Process to reduce substrate effects by forming channels under inductor devices and around analog blocks'2007 7,067,869'Adjustable 3D capacitor'2006 7,060,193'Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits'2006 6,903,013'Method to fill a trench and tunnel by using ALD seed layer and electroless plating'2005 6,902,981'Structure and process for a capacitor and other devices'2005 6,869,884'Process to reduce substrate effects by forming channels under inductor devices and around analog blocks'2005 6,852,605'Method of forming an inductor with continuous metal deposition'2005 6,821,904'Method of blocking nitrogen from thick gate oxide during dual gate CMP'2004 6,730,573'MIM and metal resistor formation at CU beol using only one extra mask'2004 6,716,693'Method of forming a surface coating layer within an opening within a body by atomic layer deposition'2004 6,709,918'Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology'2004 6,689,643'Adjustable 3D capacitor'2004 6,670,237'Method for an advanced MIM capacitor'2003 6,645,810'Method to fabricate MIM capacitor using damascene process'2003 6,624,040'Self-integrated vertical MIM capacitor in the dual damascene process'2003 6,608,362'Method and device for reducing capacitive and magnetic effects from a substrate by using a schottky diode under passive components'2003 6,548,367'Method to fabricate MIM capacitor with a curvillnear surface using damascene process'2003 6,528,838'Damascene MIM capacitor with a curvilinear surface structure'2003 6,410,376'Method to fabricate dual-metal CMOS transistors for sub-0.1 m ULSI integration'2002 6,375,857'Method to form fuse using polymeric films'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2008Patents assigned to CHARTERED SEMICONDUCTOR MFG (19)· patent assignee history

2002–2011Based in Singapore, SG· patent location history

2003Patents assigned to AGILENT TECHNOLOGIES INC (2)· patent assignee history

2003Patents assigned to CHARTERED SEMICONDUCTORS MFG L (2)· patent assignee history

2011Patents assigned to GLOBALFOUNDRIES SG PTE LTD (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
CHARTERED SEMICONDUCTOR MFG	19	2002–2008
AGILENT TECHNOLOGIES INC	2	2003
CHARTERED SEMICONDUCTORS MFG L	2	2003
GLOBALFOUNDRIES SG PTE LTD	1	2011

Locations

Location	Patents	Span
Singapore, SG	22	2002–2011