Inventor

Steven Mark Thurber

Inventor

Austin, TX, US

Overview

1996–2019

Patent span

Physics

Primary field (CPC G)

Patents· 131 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing86%

H04LTransmission of digital information, e.g. telegraphic communication11%

F41GWeapon sights1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

PatentTitleYear

10,255,194Configurable I/O address translation data structure2019 10,241,923Configurable I/O address translation data structure2019 8,935,333'Implementing multicast on a system area network channel adapter'2015 8,782,024'Managing the sharing of logical resources among separate partitions of a logically partitioned computer system'2014 8,769,168'Method for communicating with a network adapter using a queue data structure and cached address translations'2014 8,725,914'Message signaled interrupt management for a computer input/output fabric incorporating platform independent interrupt manager'2014 8,683,107'Memory mapped input/output bus address range translation'2014 8,650,349'Memory mapped input/output bus address range translation for virtual bridges'2014 8,621,120'Stalling of DMA operations in order to do memory migration using a migration in progress bit in the translation control entry mechanism'2013 8,606,984'Hierarchical to physical bus translation'2013 8,495,252'Implementing PCI-express memory domains for single root virtualized devices'2013 8,429,323'Memory mapped input/output bus address range translation'2013 8,386,679'Dynamic allocation of a direct memory address window'2013 8,364,879'Hierarchical to physical memory mapped input/output translation'2013 8,359,415'Multi-root I/O virtualization using separate management facilities of multiple logical partitions'2013 8,346,997'Use of peripheral component interconnect input/output virtualization devices to create redundant configurations'2013 8,327,055'Translating a requester identifier to a chip identifier'2012 8,316,169'Physical to hierarchical bus translation'2012 8,271,710'Moving ownership of a device between compute elements'2012 8,271,604'Initializing shared memories for sharing endpoints across a plurality of root complexes'2012 8,225,005'Use of peripheral component interconnect input/output virtualization devices to create high-speed, low-latency interconnect'2012 8,213,294'Mechanism for detecting and clearing I/O fabric lockup conditions for error recovery'2012 8,171,230'PCI express address translation services invalidation synchronization with TCE invalidation'2012 8,144,582'Differentiating blade destination and traffic types in a multi-root PCIe environment'2012 8,141,092'Management of an IOV adapter through a virtual intermediary in a hypervisor with functional management in an IOV management partition'2012 8,141,093'Management of an IOV adapter through a virtual intermediary in an IOV management partition'2012 8,141,094'Distribution of resources for I/O virtualized (IOV) adapters and management of the adapters through an IOV management partition via user selection of compatible virtual functions'2012 8,122,225'LUN masking/mapping in a SR-IOV enabled SAS adapter'2012 8,103,810'Native and non-native I/O virtualization in a single adapter'2012 7,991,839'Communication between host systems using a socket connection and shared memories'2011 7,984,454'Migration of single root stateless virtual functions'2011 7,941,568'Mapping a virtual address to PCI bus address'2011 7,937,518'Method, apparatus, and computer usable program code for migrating virtual adapters from source physical adapters to destination physical adapters'2011 7,930,598'Broadcast of shared I/O fabric error messages in a multi-host environment to all affected root nodes'2011 7,913,024'Differentiating traffic types in a multi-root PCI express environment'2011 7,907,604'Creation and management of routing table for PCI bus address based routing with integrated DID'2011 7,908,457'Retaining an association between a virtual address based buffer and a user space application that owns the buffer'2011 7,889,667'Method of routing I/O adapter error messages in a multi-host environment'2011 7,886,086'Method and apparatus for restricting input/output device peer-to-peer operations in a data processing system to improve reliability, availability, and serviceability'2011 7,860,930'Communication between host systems using a transaction protocol and shared memories'2010 7,836,129'Communication between host systems using a queuing system and shared memories'2010 7,836,238'Hot-plug/remove of a new component in a running PCIe fabric'2010 7,831,759'Method, apparatus, and computer program product for routing packets utilizing a unique identifier, included within a standard address, that identifies the destination host computer system'2010 7,827,343'Method and apparatus for providing accelerator support in a bus protocol'2010 7,813,366'Migration of a virtual endpoint from one virtual plane to another'2010 7,743,189'PCI function south-side data management'2010 7,734,843'Computer-implemented method, apparatus, and computer program product for stalling DMA operations during memory migration'2010 7,734,842'Computer-implemented method, apparatus, and computer program product for managing DMA write page faults using a pool of substitute pages'2010 7,707,465'Routing of shared I/O fabric error messages in a multi-host environment to a master control root node'2010 7,681,083'Isolation of input/output adapter error domains'2010 7,657,663'Migrating stateless virtual functions from one virtual plane to another'2010 7,636,772'Method and apparatus for dynamic retention of system area network management information in non-volatile store'2009 7,617,377'Splitting endpoint address translation cache management responsibilities between a device driver and device driver services'2009 7,590,817'Communicating with an I/O device using a queue data structure and pre-translated addresses'2009 7,587,575'Communicating with a memory registration enabled adapter using cached address translations'2009 7,571,273'Bus/device/function translation within and routing of communications packets in a PCI switched-fabric in a multi-host environment utilizing multiple root switches'2009 7,552,269'Synchronizing a plurality of processors'2009 7,549,003'Creation and management of destination ID routing structures in multi-host PCI topologies'2009 7,549,090'Autonomic recovery from hardware errors in an input/output fabric'2009 7,529,860'System and method for configuring an endpoint based on specified valid combinations of functions'2009 7,506,084'Method for communicating with an I/O adapter using cached address translations'2009 7,506,094'Method using a master node to control I/O fabric configuration in a multi-host environment'2009 7,496,045'Broadcast of shared I/O fabric error messages in a multi-host environment to all affected root nodes'2009 7,492,723'Mechanism to virtualize all address spaces in shared I/O fabrics'2009 7,484,029'Method, apparatus, and computer usable program code for migrating virtual adapters from source physical adapters to destination physical adapters'2009 7,474,623'Method of routing I/O adapter error messages in a multi-host environment'2009 7,430,630'Routing mechanism in PCI multi-host topologies using destination ID field'2008 7,398,427'Isolation of input/output adapter error domains'2008 7,395,367'Method using a master node to control I/O fabric configuration in a multi-host environment'2008 7,380,046'Method, apparatus, and computer program product for routing packets utilizing a unique identifier, included within a standard address, that identifies the destination host computer system'2008 7,363,404'Creation and management of destination ID routing structures in multi-host PCI topologies'2008 7,266,631'Isolation of input/output adapter traffic class/virtual channel and input/output ordering domains'2007 7,136,907'Method and system for informing an operating system in a system area network when a new device is connected'2006 7,134,052'Autonomic recovery from hardware errors in an input/output fabric'2006 7,113,995'Method and apparatus for reporting unauthorized attempts to access nodes in a network computing system'2006 7,103,789'Method, system, and product for indicating power status of field replaceable units'2006 7,099,955'End node partitioning using LMC for a system area network'2006 7,076,570'Method and apparatus for managing service indicator lights in a logically partitioned computer system'2006 6,990,528'System area network of end-to-end context via reliable datagram domains'2006 6,981,025'Method and apparatus for ensuring scalable mastership during initialization of a system area network'2005 6,973,510'DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge'2005 6,941,350'Method and apparatus for reliably choosing a master network manager during initialization of a network computing system'2005 6,931,471'Method, apparatus, and computer program product for migrating data subject to access by input/output devices'2005 6,851,059'Method and system for choosing a queue protection key that is tamper-proof from an application'2005 6,823,404'DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge'2004 6,748,559'Method and system for reliably defining and determining timeout values in unreliable datagrams'2004 6,718,422'Enhanced bus arbiter utilizing variable priority and fairness'2004 6,715,011'PCI/PCI-X bus bridge with performance monitor'2004 6,687,240'Transaction routing system'2004 6,654,818'DMA access authorization for 64-bit I/O adapters on PCI bus'2003 6,643,727'Isolation of I/O bus errors to a single partition in an LPAR environment'2003 6,636,947'Coherency for DMA read cached data'2003 6,629,162'System, method, and product in a logically partitioned system for prohibiting I/O adapters from accessing memory assigned to other partitions during DMA'2003 6,581,129'Intelligent PCI/PCI-X host bridge'2003 6,523,140'Computer system error recovery and fault isolation'2003 6,493,779'Method and system for interrupt handling using device pipelined packet transfers'2002 6,480,923'Information routing for transfer buffers'2002 6,480,917'Device arbitration including peer-to-peer access arbitration'2002 6,457,077'System for executing a current information transfer request even when current information transfer request exceeds current available capacity of a transit buffer'2002 6,421,756'Buffer assignment for bridges'2002 6,418,503'Buffer re-ordering system'2002 6,418,497'Method and system for interrupt handling using system pipelined packet transfers'2002 6,405,276'Selectively flushing buffered transactions in a bus bridge'2002 6,351,784'System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction'2002 6,347,349'System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction'2002 6,327,636'Ordering for pipelined read transfers'2001 6,324,612'Associating buffers in a bus bridge with corresponding peripheral devices to facilitate transaction merging'2001 6,304,984'Method and system for injecting errors to a device within a computer system'2001 6,301,630'Interrupt response in a multiple set buffer pool bus bridge'2001 6,301,627'Method/system for identifying delayed predetermined information transfer request as bypassable by subsequently-generated information transfer request using bypass enable bit in bridge translation control entry'2001 6,295,568'Method and system for supporting multiple local buses operating at different frequencies'2001 6,240,474'Pipelined read transfers'2001 6,223,299'Enhanced error handling for I/O load/store operations to a PCI device via bad parity or zero byte enables'2001 6,219,737'Read request performance of a multiple set buffer pool bus bridge'2001 6,185,642'Bus for high frequency operation with backward compatibility and hot-plug ability'2001 6,182,178'Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across a PCI host bridge supporting multiple PCI buses'2001 6,175,888'Dual host bridge with peer to peer support'2001 6,134,621'Variable slot configuration for multi-speed bus'2000 6,119,191'Performing PCI access cycles through PCI bridge hub routing'2000 6,081,863'Method and system for supporting multiple peripheral component interconnect PCI buses by a single PCI host bridge within a computer system'2000 6,035,355'PCI system and adapter requirements following reset'2000 5,978,869'Enhanced dual speed bus computer system'1999 5,898,888'Method and system for translating peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a computer system'1999 5,815,647'Error recovery by isolation of peripheral components in a data processing system'1998 5,761,462'Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data-processing system'1998 5,761,461'Method and system for preventing peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data processing system'1998 5,701,495'Scalable system interrupt structure for a multi-processing system'1997 5,694,556'Data processing system including buffering mechanism for inbound and outbound reads and posted writes'1997 5,673,399'System and method for enhancement of system bus to mezzanine bus transactions'1997 5,640,570'Information handling system for transmitting contents of line register from asynchronous controller to shadow register in another asynchronous controller determined by shadow register address buffer'1997 5,548,735'System and method for asynchronously processing store instructions to I/O space'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2019Patents assigned to IBM (131)· patent assignee history

1996–2019Based in Austin, TX, US· patent location history

2012–2014Patents assigned to THURBER STEVEN M (20)· patent assignee history

2012–2013Patents assigned to FREIMUTH DOUGLAS M (11)· patent assignee history

2012–2014Patents assigned to RECIO RENATO J (10)· patent assignee history

2012–2014Patents assigned to WOLLBRINK CURTIS C (7)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	131	1996–2019
THURBER STEVEN Mself	20	2012–2014
FREIMUTH DOUGLAS M	11	2012–2013
RECIO RENATO J	10	2012–2014
WOLLBRINK CURTIS C	7	2012–2014

Locations

Location	Patents	Span
Austin, Texas, US	131	1996–2019