Inventor
Takashi Kuroi
Inventor
Tokyo, JP
Overview
Patents· 54 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%
H10DInorganic electric semiconductor devices29%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
H10BElectronic memory devices10%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
8,592,284'Semiconductor device and manufacturing method thereof'20138,043,918'Semiconductor device and its manufacturing method'20117,791,163'Semiconductor device and its manufacturing method'20106,890,837'Method of manufacturing semiconductor device including steps of forming both insulating film and epitaxial semiconductor on substrate'20056,841,440'Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same'20056,744,113'Semiconductor device with element isolation using impurity-doped insulator and oxynitride film'20046,737,315'Method of manufacturing semiconductor device including steps of forming both insulating film and epitaxial semiconductor on substrate'20046,707,099'Semiconductor device and manufacturing method thereof'20046,667,221'Method of manufacturing semiconductor device'20036,661,066'Semiconductor device including inversely tapered gate electrode and manufacturing method thereof'20036,577,021'Static-type semiconductor memory device'20036,548,871'Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer'20036,541,825'Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same'20036,521,527'Semiconductor device and method of fabricating the same'20036,503,799'Method of manufacturing semiconductor device'20036,498,077'Semiconductor device and method of manufacturing same'20026,482,718'Method of manufacturing semiconductor device'20026,399,985'Semiconductor device'20026,383,884'Method of manufacturing semiconductor device'20026,372,604'Method for forming a trench type element isolation structure and trench type element isolation structure'20026,323,102'Method of manufacturing a semiconductor device'20016,303,432'Method of manufacturing a semiconductor device'20016,300,664'Semiconductor device and method of fabricating the same'20016,274,457'Method for manufacturing an isolation trench having plural profile angles'20016,268,263'Method of forming a trench type element isolation in semiconductor substrate'20016,265,743'Trench type element isolation structure'20016,232,187'Semiconductor device and manufacturing method thereof'20016,218,262'Semiconductor device and method of manufacturing the same'20016,180,519'Method of forming a layered wiring structure including titanium silicide'20016,162,669'Method of manufacturing a semiconductor device having an LDD structure with a recess in the source/drain region formed during removal of a damaged layer'20006,150,233'Semiconductor device and method of manufacturing the same'20006,127,737'Semiconductor device and manufacturing method thereof'20006,034,409'Isolation trench having plural profile angles'20006,017,800'Semiconductor device and method of fabricating thereof'20005,956,600'Method of manufacturing a semiconductor device'19995,950,098'Manufacturing method of a semiconductor device with a silicide layer'19995,932,912'Semiconductor device having LDD structure with a recess in the source/drain region which is formed during the removal of a damaged layer'19995,889,335'Semiconductor device and method of manufacturing the same'19995,801,425'Semiconductor device having a wiring layer including a TISI2, film of the C49 or C54 structure'19985,744,845'Complementary MOS field effect transistor with tunnel effect means'19985,710,438'Semiconductor device with a silicide layer'19985,688,701'Method of making semiconductor device having a plurality of impurity layers'19975,683,923'Semiconductor memory device capable of electrically erasing and writing information and a manufacturing method of the same'19975,616,401'Oxynitride film and its formation method, and method for forming an element isolation oxide film using the oxynitride film'19975,578,507'Method of making a semiconductor device having buried doped and gettering layers'19965,554,883'Semiconductor device and manufacturing method therefor'19965,543,647'Semiconductor device having a plurality of impurity layers'19965,538,916'Method of manufacturing semiconductor device isolation region'19965,536,665'Method of manufacturing a semiconductor device with double structured well'19965,488,245'Semiconductor memory device capable of electrically erasing and writing information'19965,455,437'Semiconductor device having crystalline defect isolation regions'19955,446,305'Semiconductor device with double structured well'19955,389,563'Method of fabricating a bipolar transistor having a high ion concentration buried floating collector'19955,341,022'Bipolar transistor having a high ion concentration buried floating collector and method of fabricating the same'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2003Patents assigned to MITSUBISHI ELECTRIC CORP (46)· patent assignee history
1994–1998Based in Itami, JP· patent location history
1995–2003Based in Hyogo, JP· patent location history
1998–2013Based in Tokyo, JP· patent location history
2004–2010Patents assigned to RENESAS TECH CORP (6)· patent assignee history
2005Based in Chiyoda-ku, JP· patent location history
2011–2013Patents assigned to RENESAS ELECTRONICS CORP (2)· patent assignee history
2013Patents assigned to HORITA KATSUYUKI (1)· patent assignee history
2013Patents assigned to ISHIBASHI MASATO (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MITSUBISHI ELECTRIC CORP | 46 | 1994–2003 |
| RENESAS TECH CORP | 6 | 2004–2010 |
| RENESAS ELECTRONICS CORP | 2 | 2011–2013 |
| HORITA KATSUYUKI | 1 | 2013 |
| ISHIBASHI MASATO | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 32 | 1998–2013 |
| Hyogo, JP | 18 | 1995–2003 |
| Itami, JP | 3 | 1994–1998 |
| Chiyoda-ku, JP | 1 | 2005 |