Inventor

Mitsugi Ogura

Inventor

Yokohama, JP

Overview

23→

Patents

1984–2017

Patent span

Electricity

Primary field (CPC H)

Patents· 23 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores20%

H10BElectronic memory devices18%

H10DInorganic electric semiconductor devices16%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests16%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

G01BMeasuring length, thickness or similar linear dimensions2%

G01RMeasuring electric variables2%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%

G06FElectric digital data processing2%

PatentTitleYear

9,627,658'Battery and battery pack'2017 5,942,784'Semiconductor device'1999 5,635,850'Intelligent test line system'1997 5,227,319'Method of manufacturing a semiconductor device'1993 5,095,463'Semiconductor memory device'1992 4,992,389'Making a self aligned semiconductor device'1991 4,881,113'Semiconductor integrated circuits with a protection device'1989 4,800,530'Semiconductor memory system with dynamic random access memory cells'1989 4,799,193'Semiconductor memory devices'1989 4,798,794'Method for manufacturing dynamic memory cell'1989 4,763,178'Semiconductor memory device'1988 4,748,596'Semiconductor memory device with sense amplifiers'1988 4,725,985'Circuit for applying a voltage to a memory cell MOS capacitor of a semiconductor memory device'1988 4,706,249'Semiconductor memory device having error detection/correction function'1987 4,688,064'Dynamic memory cell and method for manufacturing the same'1987 4,644,184'Memory clock pulse generating circuit with reduced peak current requirements'1987 4,636,981'Semiconductor memory device having a voltage push-up circuit'1987 4,630,088'MOS dynamic ram'1986 4,611,237'Semiconductor integrated circuit device'1986 4,564,854'Combined MOS/memory transistor structure'1986 4,492,973'MOS Dynamic memory cells and method of fabricating the same'1985 4,490,628'MOS Decoder selection circuit having a barrier transistor whose non-conduction period is unaffected by substrate potential disturbances'1984 4,433,911'Method of evaluating measure precision of patterns and photomask therefor'1984

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1984–1988Patents assigned to TOKYO SHIBAURA ELECTRIC CO (8)· patent assignee history

1984–1999Based in Yokohama, JP· patent location history

1986–2017Patents assigned to TOSHIBA KK (14)· patent assignee history

1989Patents assigned to KABUSHIKI KASIHA TOSHIBA (1)· patent assignee history

2017Based in Machida, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TOSHIBA KK	14	1986–2017
TOKYO SHIBAURA ELECTRIC CO	8	1984–1988
KABUSHIKI KASIHA TOSHIBA	1	1989

Locations

Location	Patents	Span
Yokohama, JP	22	1984–1999
Machida, JP	1	2017