Inventor

David R. Bearden

Inventor
Austin, TX, US

Overview

29→
Patents
1994–2017
Patent span
Physics
Primary field (CPC G)

Patents· 29 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing35%
G11CStatic stores18%
H03KPulse technique13%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
G05FSystems for regulating electric or magnetic variables8%
G01KMeasuring temperature5%
H10DInorganic electric semiconductor devices5%
G01RMeasuring electric variables3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
PatentTitleYear
9,719,861'Temperature sensor circuit'20179,528,883'Temperature sensor circuitry with scaled voltage signal'20169,367,475'System and method for cache access'20169,021,194'Memory management unit tag memory'20158,943,292'System and method for memory array access with fast address decoder'20158,710,916'Electronic circuit having shared leakage current reduction circuits'20148,566,836'Multi-core system on chip'20138,489,906'Data processor having multiple low power modes'20138,380,779'Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand'20138,365,036'Soft error correction in a memory array and method thereof'20138,319,548'Integrated circuit having low power mode voltage regulator'20128,189,408'Memory device having shifting capability and method thereof'20127,984,229'Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access'20117,843,218'Data latch with structural hold'20107,825,720'Circuit for a low power mode'20107,669,034'System and method for memory array access with fast address decoder'20107,548,103'Storage device having low power mode and methods thereof'20097,542,369'Integrated circuit having a memory with low voltage read/write operation'20097,523,373'Minimum memory operating voltage technique'20097,292,495'Integrated circuit having a memory with low voltage read/write operation'20077,215,188'Integrated circuit having a low power mode and method therefor'20077,187,205'Integrated circuit storage element having low power data retention and method therefor'20076,493,854'Method and apparatus for placing repeaters in a network of an integrated circuit'20026,480,998'Iterative, noise-sensitive method of routing semiconductor nets using a delay noise threshold'20026,067,633'Design and methodology for manufacturing data processing systems having multiple processors'20005,773,856'Structure for connecting to integrated circuitry'19985,565,386'Method of connecting to integrated circuitry'19965,373,461'Data processor a method and apparatus for performing postnormalization in a floating-point execution unit'19945,357,237'In a data processor a method and apparatus for performing a floating-point comparison operation'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2002Patents assigned to MOTOROLA INC (7)· patent assignee history
1994–2017Based in Austin, TX, US· patent location history
1996–2000Patents assigned to IBM (3)· patent assignee history
2007–2017Patents assigned to FREESCALE SEMICONDUCTOR INC (22)· patent assignee history
2012–2016Patents assigned to BEARDEN DAVID R (10)· patent assignee history
2012–2016Patents assigned to RAMARAJU RAVINDRARAJ (10)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
FREESCALE SEMICONDUCTOR INC222007–2017
BEARDEN DAVID Rself102012–2016
RAMARAJU RAVINDRARAJ102012–2016
MOTOROLA INC71994–2002
IBM31996–2000
Locations
LocationPatentsSpan
Austin, Texas, US291994–2017