LexDanaLexDanabeta
Inventor

David Jefferson

Inventor
San Jose, CA, US

Overview

64→
Patents
1994–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 64 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique40%
G06FElectric digital data processing20%
G11CStatic stores15%
H04LTransmission of digital information, e.g. telegraphic communication13%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses11%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
11,081,166Memory device random option inversion20219,208,357'FPGA configuration bitstream protection using multiple keys'20159,054,859'FPGA configuration bitstream encryption using modified key'20158,826,038'FPGA configuration bitstream protection using multiple keys'20148,750,503'FPGA configuration bitstream encryption using modified key'20148,433,930'One-time programmable memories for key storage'20138,363,833'FPGA configuration bitstream encryption using modified key'20138,271,821'Flexible RAM clock enable'20128,209,545'FPGA configuration bitstream protection using multiple keys'20127,984,292'FPGA configuration bitstream encryption using modified key'20117,864,603'Memory elements with leakage compensation'20117,818,584'One-time programmable memories for key storage'20107,734,043'Encryption key obfuscation and storage'20107,725,738'FPGA configuration bitstream protection using multiple keys'20107,606,081'Device programmable to operate as a multiplexer, demultiplexer, or memory device'20097,606,362'FPGA configuration bitstream encryption using modified key'20097,463,544'Device programmable to operate as a multiplexer, demultiplexer, or memory device'20087,397,726'Flexible RAM clock enable'20087,343,470'Techniques for sequentially transferring data from a memory device through a parallel interface'20087,236,411'Programmable memory access parameters'20077,228,451'Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuit'20077,161,381'Multiple size memories in a programmable logic device'20077,051,153'Memory array operating as a shift register'20066,996,736'Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuit'20066,965,249'Programmable logic device with redundant circuitry'20056,879,183'Programmable logic device architectures with super-regions having logic regions and a memory region'20056,826,741'Flexible I/O routing resources'20046,815,981'Programmable logic array integrated circuit devices'20046,798,242'Programmable logic device with hierarchical interconnection resources'20046,759,871'Line segmentation in programmable logic devices having redundancy circuitry'20046,720,796'Multiple size memories in a programmable logic device'20046,657,456'Programmable logic with on-chip DLL or PLL to distribute clock'20036,600,337'Line segmentation in programmable logic devices having redundancy circuitry'20036,577,160'Programmable logic device with hierarchical interconnection resources'20036,480,028'Programmable logic device architectures with super-regions having logic regions and memory region'20026,459,303'High speed programmable address decoder'20026,417,694'Programmable logic device with hierarchical interconnection resources'20026,392,438'Programmable logic array integrated circuit devices'20026,337,578'Redundancy circuitry for programmable logic devices with interleaved input circuits'20026,326,812'Programmable logic device with logic signal delay compensated clock network'20016,300,794'Programmable logic device with hierarchical interconnection resources'20016,292,016'Programmable logic with on-chip DLL or PLL to distribute clock'20016,278,288'Programmable logic device with enhanced multiplexing capabilities in interconnect resources'20016,262,933'High speed programmable address decoder'20016,225,823'Input/output circuitry for programmable logic devices'20016,222,382'Redundancy circuitry for programmable logic devices with interleaved input circuits'20016,215,326'Programmable logic device architecture with super-regions having logic regions and a memory region'20016,163,195'Temperature compensated delay chain'20006,130,552'Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution'20006,127,865'Programmable logic device with logic signal delay compensated clock network'20006,121,790'Programmable logic device with enhanced multiplexing capabilities in interconnect resources'20006,115,312'Programmable logic device memory cell circuit'20006,107,820'Redundancy circuitry for programmable logic devices with interleaved input circuits'20006,107,825'Input/output circuitry for programmable logic devices'20006,094,064'Programmable logic device incorporating and input/output overflow bus'20005,977,793'Programmable logic device with hierarchical interconnection resources'19995,963,069'System for distributing clocks using a delay lock loop in a programmable logic circuit'19995,850,152'Programmable logic array integrated circuit devices'19985,850,151'Programmable logic array intergrated circuit devices'19985,847,617'Variable-path-length voltage-controlled oscillator circuit'19985,744,991'System for distributing clocks using a delay lock loop in a programmable logic circuit'19985,699,020'Phase latched differential charge pump circuit and method'19975,642,082'Loop filter level detection circuit and method'19975,293,623'Random access memory based buffer memory and associated method utilizing pipelined look-ahead reading'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994Based in Milpitas, CA, US· patent location history
1997–2015Patents assigned to ALTERA CORP (62)· patent assignee history
1997–2005Based in San Jose, CA, US· patent location history
2000–2015Based in Morgan Hill, CA, US· patent location history
2011Based in Morgan Hills, CA, US· patent location history
2012–2014Patents assigned to JEFFERSON DAVID (4)· patent assignee history
2012–2014Patents assigned to JOYCE JUJU (4)· patent assignee history
2012–2014Patents assigned to LANGHAMMER MARTIN (4)· patent assignee history
2012–2014Patents assigned to STREICHER KEONE (4)· patent assignee history
2021Based in Meridian, ID, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ALTERA CORP621997–2015
JEFFERSON DAVIDself42012–2014
JOYCE JUJU42012–2014
LANGHAMMER MARTIN42012–2014
STREICHER KEONE42012–2014
Locations
LocationPatentsSpan
San Jose, California, US331997–2005
Morgan Hill, California, US282000–2015
Meridian, ID, US12021
Morgan Hills, California, US12011
Milpitas, California, US11994