Inventor

Howard L. Kalter

Inventor

Colchester, VT, US

Overview

1976–2004

Patent span

Electricity

Primary field (CPC H)

Patents· 64 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores20%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%

H10BElectronic memory devices16%

H10DInorganic electric semiconductor devices13%

G06FElectric digital data processing8%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%

H03KPulse technique7%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%

G01RMeasuring electric variables4%

H04LTransmission of digital information, e.g. telegraphic communication1%

PatentTitleYear

6,730,529'Method for chip testing'2004 6,440,801'Structure for folded architecture pillar memory cell'2002 6,429,080'Multi-level dram trench store utilizing two capacitors and two plates'2002 6,426,904'Structures for wafer level test and burn-in'2002 6,369,671'Voltage controlled transmission line with real-time adaptive control'2002 6,345,380'Interconnected integrated circuits having reduced inductance during switching and a method of interconnecting such circuits'2002 6,316,309'Method of forming self-isolated and self-aligned 4F-square vertical FET-trench DRAM cells'2001 6,294,942'Method and apparatus for providing self-terminating signal lines'2001 6,282,115'Multi-level DRAM trench store utilizing two capacitors and two plates'2001 6,255,899'Method and apparatus for increasing interchip communications rates'2001 6,233,184'Structures for wafer level test and burn-in'2001 6,177,809'Redundant input/output driver circuit'2001 6,177,818'Complementary depletion switch body stack off-chip driver'2001 6,137,128'Self-isolated and self-aligned 4F-square vertical fet-trench dram cells'2000 6,114,725'Structure for folded architecture pillar memory cell'2000 6,087,199'Method for fabricating a very dense chip package'2000 6,077,745'Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array'2000 6,044,024'Interactive method for self-adjusted access on embedded DRAM memory macros'2000 6,034,389'Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array'2000 6,013,548'Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array'2000 5,998,868'Very dense chip package'1999 5,972,745'Method or forming self-aligned halo-isolated wells'1999 5,961,653'Processor based BIST for an embedded memory'1999 5,929,477'Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array'1999 5,925,924'Methods for precise definition of integrated circuit chip edges'1999 5,899,703'Method for chip testing'1999 5,875,470'Multi-port multiple-simultaneous-access DRAM chip'1999 5,866,443'Very dense integrated circuit package and method for forming the same'1999 5,814,885'Very dense integrated circuit package'1998 5,796,662'Integrated circuit chip with a wide I/O memory array and redundant data lines'1998 5,770,884'Very dense integrated circuit package'1998 5,702,984'Integrated mulitchip memory module, structure and fabrication'1997 5,691,248'Methods for precise definition of integrated circuit chip edges'1997 5,682,394'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'1997 5,663,924'Boundary independent bit decode for a SDRAM'1997 5,656,544'Process for forming a polysilicon electrode in a trench'1997 5,648,684'Endcap chip with conductive, monolithic L-connect for multichip stack'1997 5,581,567'Dual level error detection and correction employing data subsets from previously corrected data'1996 5,571,754'Method of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack'1996 5,563,086'Integrated memory cube, structure and fabrication'1996 5,561,622'Integrated memory cube structure'1996 5,533,036'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'1996 5,463,335'Power up detection circuits'1995 5,426,566'Multichip integrated circuit packages and systems'1995 5,399,516'Method of making shadow RAM cell having a shallow trench EEPROM'1995 5,270,261'Three dimensional multichip package methods of fabrication'1993 5,241,500'Method for setting test voltages in a flash write mode'1993 5,228,046'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'1993 5,202,754'Three-dimensional multichip packages and methods of fabrication'1993 5,196,722'Shadow ram cell having a shallow trench eeprom'1993 5,134,616'Dynamic RAM with on-chip ECC and optimized bit and word redundancy'1992 5,058,115'Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature'1991 5,031,151'Wordline drive inhibit circuit implementing worldline redundancy without an access time penalty'1991 5,015,880'CMOS driver circuit'1991 5,010,524'Crosstalk-shielded-bit-line dram'1991 4,999,815'Low power addressing systems'1991 4,782,250'CMOS off-chip driver circuits'1988 4,603,341'Stacked double dense read only memory'1986 4,566,022'Flexible/compressed array macro design'1986 4,506,341'Interlaced programmable logic array having shared elements'1985 4,375,085'Dense electrically alterable read only memory'1983 4,363,110'Non-volatile dynamic RAM cell'1982 4,021,789'Self-aligned integrated circuits'1977 3,993,917'Parameter independent FET sense amplifier'1976

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1976–2004Patents assigned to IBM (63)· patent assignee history

1976–2004Based in Colchester, VT, US· patent location history

1999Based in Chittenden County, VT, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	63	1976–2004

Locations

Location	Patents	Span
Colchester, VT, US	63	1976–2004
Chittenden County, VT, US	1	1999