Inventor
Charles A. Kilmer
Inventor
Essex Junction, VT, US
Overview
Patents· 52 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores43%
G06FElectric digital data processing39%
H03MCoding10%
H01LSemiconductor devices2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
H01RElectrically-conductive connections1%
PatentTitleYear
10,497,409Implementing DRAM row hammer avoidance201910,453,503Implementing DRAM row hammer avoidance201910,102,884Distributed serialized data buffer and a memory module for a cascadable and extended memory subsystem201810,063,263Extended error correction coding data storage201810,032,505Dynamic random access memory with pseudo differential sensing201810,027,349Extended error correction coding data storage201810,019,312Error monitoring of a memory device containing embedded error correction20189,965,346Handling repaired memory array elements in a memory of a computer system20189,940,457Detecting a cryogenic attack on a memory device with embedded error correction20189,917,601'Adaptive error correction in a memory system'20189,880,896'Error feedback and logging with memory on-chip error checking and correcting (ECC)'20189,760,504'Nonvolatile memory data security'20179,747,148'Error monitoring of a memory device containing embedded error correction'20179,734,095'Nonvolatile memory data security'20179,733,870'Error vector readout from a memory device'20179,734,008'Error vector readout from a memory device'20179,690,649'Memory device error history bit'20179,684,555'Selective memory error reporting'20179,626,242'Memory device error history bit'20179,607,716'Detecting defective connections in stacked memory devices'20179,606,851'Error monitoring of a memory device containing embedded error correction'20179,495,242'Adaptive error correction in a memory system'20169,471,423'Selective memory error reporting'20169,471,422'Adaptive error correction in a memory system'20169,454,422'Error feedback and logging with memory on-chip error checking and correcting (ECC)'20169,298,395'Memory system connector'20169,263,157'Detecting defective connections in stacked memory devices'20169,251,894'Accessing a resistive memory storage device'20169,189,327'Error-correcting code distribution for memory systems'20159,159,410'Accessing a resistive memory storage device'20159,146,882'Securing the contents of a memory device'20159,146,883'Securing the contents of a memory device'20159,087,612'DRAM error detection, evaluation, and correction'20159,064,602'Implementing memory device with sub-bank architecture'20159,058,896'DRAM refresh'20159,037,930'Managing errors in a DRAM by weak cell encoding'20159,001,609'Hybrid latch and fuse scheme for memory repair'20158,995,217'Hybrid latch and fuse scheme for memory repair'20158,898,544'DRAM error detection, evaluation, and correction'20148,887,014'Managing errors in a DRAM by weak cell encoding'20148,848,471'Method for optimizing refresh rate for DRAM'20148,799,566'Memory system with a programmable refresh cycle'20148,659,959'Advanced memory device having improved performance, reduced power and increased reliability'20148,452,919'Advanced memory device having improved performance, reduced power and increased reliability'20138,307,270'Advanced memory device having improved performance, reduced power and increased reliability'20127,984,329'System and method for providing DRAM device-level repair via address remappings external to the device'20117,948,817'Advanced memory device having reduced power and improved performance'20117,717,752'276-pin buffered memory module with enhanced memory system interconnect and features'20106,799,291'Method and system for detecting a hard failure in a memory array'20046,785,837'Fault tolerant memory system utilizing memory arrays with hard error detection'20046,732,291'High performance fault tolerant memory system utilizing greater than four-bit data word memory arrays'20046,728,156'Memory array system'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2019Patents assigned to IBM (52)· patent assignee history
2004–2019Based in Essex Junction, VT, US· patent location history
2004Based in Chittenden County, VT, US· patent location history
2012–2015Patents assigned to KILMER CHARLES A (6)· patent assignee history
2012–2015Patents assigned to KIM KYU-HYOUN (6)· patent assignee history
2012–2014Patents assigned to HUNTER HILLERY C (4)· patent assignee history
2012–2014Patents assigned to MAULE WARREN E (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 52 | 2004–2019 |
| KILMER CHARLES Aself | 6 | 2012–2015 |
| KIM KYU-HYOUN | 6 | 2012–2015 |
| HUNTER HILLERY C | 4 | 2012–2014 |
| MAULE WARREN E | 4 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 51 | 2004–2019 |
| Chittenden County, VT, US | 1 | 2004 |