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Inventor

Mitrajit Chatterjee

Inventor
San Jose, CA, US

Overview

5→
Patents
2005–2019
Patent span
Physics
Primary field (CPC G)

Patents· 5 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing80%
G11CStatic stores20%
PatentTitleYear
10,204,698Method to dynamically inject errors in a repairable memory on silicon and a method to validate built-in-self-repair logic20198,397,197'Integrated circuit module time delay budgeting'20137,827,555'Scheduler for a multiprocessing computing system'20107,386,774'Memory unit with controller managing memory access through JTAG and CPU interfaces'20086,865,638'Apparatus and method for transferring multi-byte words in a fly-by DMA operation'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2010Patents assigned to INTEGRATED DEVICE TECH (3)· patent assignee history
2005–2013Based in San Jose, CA, US· patent location history
2010–2019Based in Santa Clara, CA, US· patent location history
2013Patents assigned to APPLIED MICRO CIRCUITS CORP (1)· patent assignee history
2013Patents assigned to BADIDA SANDEEP (1)· patent assignee history
2013Patents assigned to CHATTERJEE MITRAJIT (1)· patent assignee history
2019Patents assigned to AMPERE COMPUTING LLC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEGRATED DEVICE TECH32005–2010
AMPERE COMPUTING LLC12019
APPLIED MICRO CIRCUITS CORP12013
BADIDA SANDEEP12013
CHATTERJEE MITRAJITself12013
Locations
LocationPatentsSpan
San Jose, California, US32005–2013
Santa Clara, California, US22010–2019