Inventor
Yu-chao LIN
Inventor
TW
Overview
Patents· 59 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Nprimary
H10NElectric solid-state devices not otherwise provided for23%
H10BElectronic memory devices20%
H01LSemiconductor devices20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
H10DInorganic electric semiconductor devices8%
B82YSpecific uses or applications of nanostructures6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
G11CStatic stores3%
B01DSeparation2%
H10KOrganic electric solid-state devices2%
PatentTitleYear
12,507,600—202512,489,370Low power consumption feedback circuit for power supply device202512,471,507Memory device and fabrication method thereof202512,431,784Controller for power supply device202512,426,276Semiconductor device, memory cell and method of forming the same202512,408,565Phase-change memory devices202512,336,192Method of forming semiconductor device202512,324,362Phase-change memory device and method202512,317,761Phase-change memory device and method for fabricating the same202512,317,515Memory device and semiconductor die having the memory device202512,310,049Semiconductor device structure with nanostructure202512,256,654Memory cell, method of forming the same, and semiconductor device having the same202512,245,526Sidewall protection for PCRAM device202512,237,421Semiconductor device structure and method for forming the same202512,238,933Semiconductor structures and methods of forming the same202512,239,031Memory cell, semiconductor device having the same, and methods of manufacturing the same202512,211,844Semiconductor structure202512,213,388Memory cell, integrated circuit, and manufacturing method of memory cell202512,161,055Memory array, semiconductor chip and manufacturing method of memory array202412,151,213Method of manufacturing semiconductor devices including the steps of removing one or more of the nanotubes from the stack of nanotubes, and/or removing spacers that surrounds each of the plurality of nanotubes, and forming gate dielectric and/or gate electrode to the nanotubes202412,156,485Memory cell and semiconductor device having the same202412,144,268Semiconductor structure and method of manufacture202412,142,521Interconnect structure and semiconductor device having the same202412,133,476Phase change memory device having tapered portion of the bottom memory layer202412,120,968Semiconductor device, memory cell including connecting structure having base portion and pillar portion, and method of forming the same202412,102,018Memory stacks and methods of forming the same202412,094,771Interconnect structure and method202412,040,400Method for forming semiconductor device structure with nanostructure202412,041,790Semiconductor device, memory cell and method of forming the same202412,010,928Memory cell, semiconductor device having the same, and methods of manufacturing the same202411,997,933Phase-change memory device and method202411,957,070Semiconductor device, memory cell and method of forming the same202411,935,958Semiconductor device structure and method for forming the same202411,925,127Phase-change memory device and method202411,864,477Memory cell, method of forming the same, and semiconductor device having the same202411,825,753Memory cell, integrated circuit, and manufacturing method of memory cell202311,818,967Sidewall protection for PCRAM device202311,805,712Phase change memory device having tapered portion of the bottom memory layer202311,793,092Memory stacks and methods of forming the same202311,749,528Method of manufacturing semiconductor devices including the steps of removing a plurality of spacers that surrounds each of the plurality of nanotubes into a layer of nanotubes, and forming gate dielectric and/or gate electrode202311,737,287Memory device, method of forming the same, and semiconductor device having the same202311,647,682Memory array, semiconductor chip and manufacturing method of memory array202311,616,146Semiconductor device structure and method for forming the same202311,594,576Semiconductor device, memory cell and method of forming the same202311,588,106Method to effectively suppress heat dissipation in PCRAM devices202311,545,490Semiconductor structure and method for forming the same202311,489,113Semiconductor device, memory cell and method of forming the same202211,456,211Method of forming interconnect structure202211,450,563Interconnect structure and method202211,411,181Phase-change memory device and method202211,411,180Phase-change memory device and method202211,404,635Memory stacks and methods of forming the same202211,393,925Semiconductor device structure with nanostructure202211,362,277Sidewall protection for PCRAM device202211,342,181Semiconductor devices and methods of manufacture202211,342,501Memory cell, method of forming the same, and semiconductor device having the same202211,322,619Semiconductor device structure and method for forming the same202211,283,011Phase change memory device having tapered portion of the bottom memory layer202211,245,071Memory cell, method of forming the same, and semiconductor device having the same2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2025Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (57)· patent assignee history
2022–2025Based in TW· patent location history
2025Patents assigned to POWER FOREST TECH CORPORATION (2)· patent assignee history
2025Patents assigned to TAIWAN SEMICONDCUTOR MFG COMPANY LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 57 | 2022–2025 |
| POWER FOREST TECH CORPORATION | 2 | 2025 |
| TAIWAN SEMICONDCUTOR MFG COMPANY LTD | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 59 | 2022–2025 |