Inventor

Jean-Pierre Colinge

Inventor

Hsinchu, TW

Overview

1988–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 139 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices30%

H01LSemiconductor devices28%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%

B82YSpecific uses or applications of nanostructures9%

H10BElectronic memory devices4%

G11CStatic stores2%

G06FElectric digital data processing1%

H10KOrganic electric solid-state devices0%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests0%

PatentTitleYear

11,133,404FinFET device including a stem region of a fin element2021 11,127,734Vertical nanowire transistor for input/output structure2021 11,104,573Semiconductor arrangement with one or more semiconductor columns2021 11,043,597Method for reducing contact resistance in semiconductor structures2021 11,038,052Semiconductor arrangement with one or more semiconductor columns2021 10,985,159Method for manufacturing monolithic three-dimensional (3D) integrated circuits2021 10,964,691Method for manufacturing monolithic three-dimensional (3D) integrated circuits2021 10,943,833Silicon and silicon germanium nanowire formation2021 10,872,776Structure and formation method of semiconductor device structure2020 10,854,721Semiconductor device with silicide2020 10,854,735Method of forming transistor2020 10,847,736Method of manufacturing a semiconductor device and a semiconductor device2020 10,818,780Devices having a semiconductor material that is semimetal in bulk and methods of forming the same2020 10,763,198Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure2020 10,734,503Asymmetric semiconductor device2020 10,714,601Fabrication of a transistor with a channel structure and semimetal source and drain regions2020 10,714,349Semiconductor device and manufacturing method thereof2020 10,705,7663D cross-bar nonvolatile memory2020 10,699,964Silicon and silicon germanium nanowire formation2020 10,644,1682-D material transistor with vertical structure2020 10,559,563Method for manufacturing monolithic three-dimensional (3D) integrated circuits2020 10,529,729Non-volatile memory device having nanocrystal floating gate and method of fabricating same2020 10,510,744Vertical nanowire transistor for input/output structure2019 10,497,792Contacts for highly scaled transistors2019 10,461,179Devices having a semiconductor material that is semimetal in bulk and methods of forming the same2019 10,461,176FinFET device including a stem region of a fin element2019 10,461,190Method for reducing contact resistance in semiconductor structures2019 10,453,522SRAM with stacked bit cells2019 10,361,270Nanowire MOSFET with different silicides on source and drain2019 10,325,989Semiconductor device with silicide2019 10,294,101Semiconductor arrangement with one or more semiconductor columns2019 10,290,737Semiconductor arrangement with one or more semiconductor columns2019 10,276,664Semiconductor structures and methods for multi-dimension of nanowire diameter to improve drive current2019 10,269,572Semiconductor device and manufacturing method thereof2019 10,193,090Method of manufacturing a semiconductor device and a semiconductor device2019 10,191,6943D cross-bar nonvolatile memory2019 10,170,404Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure2019 10,164,061Method of fabricating non-volatile memory device array2018 10,163,729Silicon and silicon germanium nanowire formation2018 10,164,105Forming conductive STI liners for FinFETs2018 10,164,040Gate structure and method for fabricating the same2018 10,157,928Semiconductor devices and methods of manufacture thereof2018 10,134,9152-D material transistor with vertical structure2018 10,134,918Memory device and method for fabricating the same2018 10,083,869Stacked device and associated layout structure2018 10,062,779Semiconductor device and manufacturing method thereof2018 10,026,826Method of forming semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric2018 10,008,253Array architecture and write operations of thyristor based random access memory2018 10,008,566Semiconductor device with reduced electrical resistance and capacitance2018 10,002,922Process to etch semiconductor materials2018 9,978,863Semiconductor arrangement with one or more semiconductor columns2018 9,941,404Tuning strain in semiconductor devices2018 9,941,374Contacts for highly scaled transistors2018 9,935,016Silicon and silicon germanium nanowire formation2018 9,935,198Method for inducing strain in vertical semiconductor columns2018 9,929,245'Semiconductor structures and methods for multi-level work function'2018 9,929,269'FinFET having an oxide region in the source/drain region'2018 9,929,257'Devices having a semiconductor material that is semimetal in bulk and methods of forming the same'2018 9,899,398'Non-volatile memory device having nanocrystal floating gate and method of fabricating same'2018 9,899,490'Semiconductor structure with changeable gate length and method for forming the same'2018 9,893,189'Method for reducing contact resistance in semiconductor structures'2018 9,875,902Semiconductor device and manufacturing method thereof2018 9,871,141'Thermally tuning strain in semiconductor devices'2018 9,865,655'Memory cell structure with resistance-change material and method for forming the same'2018 9,853,150Method of fabricating epitaxial gate dielectrics and semiconductor device of the same2017 9,825,043'Semiconductor devices and methods of manufacture thereof'2017 9,786,774'Metal gate of gate-all-around transistor'2017 9,779,959'Structure and formation method of semiconductor device structure'2017 9,773,868'Nanowire MOSFET with support structures for source and drain'2017 9,764,950'Semiconductor arrangement with one or more semiconductor columns'2017 9,735,255'Method for fabricating a finFET device including a stem region of a fin element'2017 9,735,146'Vertical nanowire transistor for input/output structure'2017 9,728,602'Variable channel strain of nanowire transistors to improve drive current'2017 9,698,270'FinFET with dual workfunction gate structure'2017 9,691,695'Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure'2017 9,680,012'Semiconductor device structure and method for forming the same'2017 9,673,209'Memory device and method for fabricating the same'2017 9,660,107'3D cross-bar nonvolatile memory'2017 9,659,632'SRAM with stacked bit cells'2017 9,653,457'Stacked device and associated layout structure'2017 9,653,604'Semiconductor device and manufacturing method thereof'2017 9,647,117'Apparatus and method for forming semiconductor contacts'2017 9,640,645'Semiconductor device with silicide'2017 9,634,132'Semiconductor structures and methods for multi-level band gap energy of nanowire transistors to improve drive current'2017 9,634,091'Silicon and silicon germanium nanowire formation'2017 9,620,591'Semiconductor structures and methods for multi-level work function and multi-valued channel doping of nanowire transistors to improve drive current'2017 9,620,422'Semiconductor arrangement'2017 9,614,059'Forming conductive STI liners for FinFETs'2017 9,614,091'Gate structure and method for fabricating the same'2017 9,570,579'Semiconductor structures and methods for multi-level work function'2017 9,564,431'Semiconductor structures and methods for multi-level work function'2017 9,564,493'Devices having a semiconductor material that is semimetal in bulk and methods of forming the same'2017 9,508,858'Contacts for highly scaled transistors'2016 9,490,348'Method of forming a FinFET having an oxide region in the source/drain region'2016 9,484,460'Semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric'2016 9,478,624'Self-aligned wrapped-around structure'2016 9,466,668'Inducing localized strain in vertical nanowire transistors'2016 9,425,324'Semiconductor device and channel structure thereof'2016 9,419,003'Semiconductor devices and methods of manufacture thereof'2016 9,419,098'Tuning strain in semiconductor devices'2016 9,412,828'Aligned gate-all-around structure'2016 9,368,619'Method for inducing strain in vertical semiconductor columns'2016 9,356,020'Semiconductor arrangement'2016 9,349,850'Thermally tuning strain in semiconductor devices'2016 9,343,551'Methods for manufacturing a fin structure of semiconductor device'2016 9,299,810'Fin-type field effect transistor and method of fabricating the same'2016 9,275,910'Semiconductor-on-insulator structure and method of fabricating the same'2016 9,276,114'FinFET with dual workfunction gate structure'2016 9,263,535'Method for fabricating a gate all around device'2016 9,263,295'Nanowire MOSFET with support structures for source and drain'2016 9,224,849'Transistors with wrapped-around gates and methods for forming the same'2015 9,219,115'Forming conductive STI liners for FinFETS'2015 9,209,247'Self-aligned wrapped-around structure'2015 9,209,022'Semiconductor structure including laterally disposed layers having different crystal orientations and method of fabricating the same'2015 9,196,730'Variable channel strain of nanowire transistors to improve drive current'2015 9,190,473'Apparatus and method for forming semiconductor contacts'2015 9,184,269'Silicon and silicon germanium nanowire formation'2015 9,177,924'Vertical nanowire transistor for input/output structure'2015 9,147,753'FinFET having uniform doping profile and method of forming the same'2015 9,111,996'Semiconductor-on-insulator structure and method of fabricating the same'2015 9,048,301'Nanowire MOSFET with support structures for source and drain'2015 9,034,717'Semiconductor-on-insulator structure and method of fabricating the same'2015 9,006,829'Aligned gate-all-around structure'2015 9,006,786'Fin structure of semiconductor device'2015 9,006,842'Tuning strain in semiconductor devices'2015 8,999,805'Semiconductor device with reduced gate length'2015 8,963,206'Method for increasing fin density'2015 8,823,060'Method for inducing strain in FinFET channels'2014 8,815,691'Method of fabricating a gate all around device'2014 8,772,109'Apparatus and method for forming semiconductor contacts'2014 8,178,862'Junctionless metal-oxide-semiconductor transistor'2012 7,253,043'Short channel semiconductor device fabrication'2007 6,391,752'Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane'2002 6,359,311'Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same'2002 5,272,369'Circuit element with elimination of kink effect'1993 5,233,236'Method and device for compensating drift in a semiconductor element'1993 4,857,476'Bipolar transistor process using sidewall spacer for aligning base insert'1989 4,810,664'Method for making patterned implanted buried oxide transistors and structures'1989 4,725,561'Process for the production of mutually electrically insulated monocrystalline silicon islands using laser recrystallization'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989Patents assigned to HEWLETT PACKARD CO (2)· patent assignee history

1989Based in Palo Alto, CA, US· patent location history

1993Patents assigned to IMEC INTER UNI MICRO ELECTR (2)· patent assignee history

1993Based in Louvain-la-Neuve, BE· patent location history

2002–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (30)· patent assignee history

2002–2007Based in Carmichael, CA, US· patent location history

2012–2015Patents assigned to COLINGE JEAN-PIERRE (3)· patent assignee history

2014–2021Based in Hsinchu, TW· patent location history

2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (101)· patent assignee history

2020Based in Grenoble, FR· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	101	2015–2021
TAIWAN SEMICONDUCTOR MFG	30	2002–2016
COLINGE JEAN-PIERREself	3	2012–2015
HEWLETT PACKARD CO	2	1989
IMEC INTER UNI MICRO ELECTR	2	1993

Locations

Location	Patents	Span
Hsinchu, TW	129	2014–2021
Carmichael, California, US	3	2002–2007
Louvain-la-Neuve, BE	2	1993
Palo Alto, California, US	2	1989
Grenoble, FR	1	2020