Inventor
Ali S. Oztaskin
Inventor
Beaverton, OR, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing71%
H04LTransmission of digital information, e.g. telegraphic communication13%
H04NPictorial communication, e.g. television8%
G06TImage data processing or generation, in general4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
PatentTitleYear
9,507,752'Methods, apparatus and systems for facilitating RDMA operations with reduced doorbell rings'20168,504,795'Method, system, and program for utilizing a virtualized data structure table'20137,853,957'Doorbell mechanism using protection domains'20107,702,826'Method and apparatus by utilizing platform support for direct memory access remapping by remote DMA (“RDMAâ€)-capable devices'20107,694,100'Managing system memory resident device management queues'20107,487,284'Transaction flow and ordering for a packet processing engine, located within an input-output hub'20097,263,568'Interrupt system using event data structures'20076,347,362'Flexible event monitoring counters in multi-node processor systems and process of operating the same'20026,115,796'Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions'20006,085,325'Method and apparatus for supporting power conservation operation modes'20006,058,440'Programmable and adaptive resource allocation device and resource use recorder'20005,982,425'Method and apparatus for draining video data from a planarized video buffer'19995,941,960'Host initiated PCI burst writes utilizing posted write buffers'19995,923,193'Method and apparatus for transferring signals between multiple clock timing domains'19995,897,667'Method and apparatus for transferring data received from a first bus in a non-burst manner to a second bus in a burst manner'19995,838,387'Digital video scaling engine'19985,768,626'Method and apparatus for servicing a plurality of FIFO\'s in a capture gate array'19985,630,094'Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions'19975,559,965'Input/output adapter cards having a plug and play compliant mode and an assigned resources mode'19965,479,647'Clock generation and distribution system for a memory controller with a CPU interface for synchronizing the CPU interface with a microprocessor external to the memory controller'19955,463,744'Emulation of slower speed processor'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2016Patents assigned to INTEL CORP (21)· patent assignee history
1995–2016Based in Beaverton, OR, US· patent location history
1995Based in Hillsboro, OR, US· patent location history
2013Patents assigned to OZTASKIN ALI S (1)· patent assignee history
2013Patents assigned to SHAH HEMAL V (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 21 | 1995–2016 |
| OZTASKIN ALI Sself | 1 | 2013 |
| SHAH HEMAL V | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 20 | 1995–2016 |
| Hillsboro, OR, US | 1 | 1995 |