Inventor

Gilbert Neiger

Inventor

Portland, OR, US

Overview

2000–2021

Patent span

Physics

Primary field (CPC G)

Patents· 166 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing92%

H04LTransmission of digital information, e.g. telegraphic communication4%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%

G11CStatic stores1%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%

PatentTitleYear

11,113,217Delivering interrupts to user-level applications2021 11,099,880Virtualization of process address space identifiers for scalable virtualization of input/output devices2021 11,093,277Systems, methods, and apparatuses for heterogeneous computing2021 11,048,512Apparatus and method to identify the source of an interrupt2021 11,048,588Monitoring the operation of a processor2021 11,023,233Methods, apparatus, and instructions for user level thread suspension2021 11,019,061Protecting supervisor mode information2021 10,999,284Protecting supervisor mode information2021 10,901,772Virtualization exceptions2021 10,768,968Split-control of page attributes between virtual machines and a virtual machine monitor2020 10,747,682Synchronizing a translation lookaside buffer with an extended paging table2020 10,740,249Maintaining processor resources during architectural events2020 10,713,195Interrupts between virtual machines2020 10,713,177Defining virtualized page attributes based on guest page attributes2020 10,705,976Scalable processor-assisted guest physical address translation2020 10,678,575Instruction-set support for invocation of VMM-configured services without VMM intervention2020 10,671,737Cryptographic memory ownership table for secure public cloud2020 10,657,071System, apparatus and method for page granular, software controlled multiple key memory encryption2020 10,628,612Secure public cloud with protected guest-verified host control2020 10,599,455Virtualization event processing in a layered virtualization architecture2020 10,599,547Monitoring the operation of a processor2020 10,572,415Delivering interrupts to user-level applications2020 10,515,023System for address mapping and translation protection2019 10,503,664Virtual machine manager for address mapping and translation protection2019 10,503,662Systems, apparatuses, and methods for implementing temporary escalated privilege2019 10,489,309Memory protection key architecture with independent user and supervisor domains2019 10,394,595Method to manage guest address space trusted by virtual machine monitor2019 10,303,899Secure public cloud with protected guest-verified host control2019 10,303,620Maintaining processor resources during architectural events2019 10,296,366Virtualization exceptions2019 10,235,301Dynamic page table edit control2019 10,180,911Synchronizing a translation lookaside buffer with an extended paging table2019 10,175,990Gathering and scattering multiple data elements2019 10,135,825Protecting supervisor mode information2018 10,114,768Enhance memory access permission based on per-page current privilege level2018 10,114,767Virtualizing physical memory in a virtual machine system using a hierarchy of extended page tables to translate guest-physical addresses to host-physical addresses2018 10,114,651Gathering and scattering multiple data elements2018 10,002,012Virtualization event processing in a layered virtualization architecture2018 9,996,475Maintaining processor resources during architectural events2018 9,971,615Optimizing processor-managed resources based on the behavior of a virtual machine monitor2018 9,921,984'Delivering interrupts to user-level applications'2018 9,916,257'Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory'2018 9,910,699'Virtual processor direct interrupt delivery mechanism'2018 9,898,330'Compacted context state management'2018 9,892,069'Posting interrupts to virtual processors'2018 9,858,167'Monitoring the operation of a processor'2018 9,804,870'Instruction-set support for invocation of VMM-configured services without VMM intervention'2017 9,804,871'Instruction-set support for invocation of VMM-configured services without VMM intervention'2017 9,792,222'Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure'2017 9,785,485'Virtualization event processing in a layered virtualization architecture'2017 9,740,644'Avoiding premature enabling of nonmaskable interrupts when returning from exceptions'2017 9,710,393'Dynamic page table edit control'2017 9,678,890'Synchronizing a translation lookaside buffer with an extended paging table'2017 9,563,455'Virtualization exceptions'2017 9,507,730'Maintaining processor resources during architectural events'2016 9,471,494'Method and apparatus for cache line write back operation'2016 9,442,868'Delivering interrupts directly to a virtual processor'2016 9,423,959'Method and apparatus for store durability and ordering in a persistent memory architecture'2016 9,405,570'Low latency virtual machine page table management'2016 9,405,565'Virtualization event processing in a layered virtualization architecuture'2016 9,372,806'Synchronizing a translation lookaside buffer with an extended paging table'2016 9,372,807'Synchronizing a translation lookaside buffer with an extended paging table'2016 9,335,943'Method and apparatus for fine grain memory protection'2016 9,329,884'Managing generated trace data for a virtual machine'2016 9,330,021'Synchronizing a translation lookaside buffer with an extended paging table'2016 9,323,533'Supervisor mode execution protection'2016 9,298,640'Synchronizing a translation lookaside buffer with an extended paging table'2016 9,298,641'Synchronizing a translation lookaside buffer with an extended paging table'2016 9,262,338'Synchronizing a translation lookaside buffer with an extended paging table'2016 9,251,094'Synchronizing a translation lookaside buffer with an extended paging table'2016 9,244,712'Virtualizing performance counters'2016 9,239,801'Systems and methods for preventing unauthorized stack pivoting'2016 9,235,434'Virtualization event processing in a layered virtualization architecture'2016 9,164,918'Maintaining processor resources during architectural events'2015 9,164,920'Using permission bits in translating guests virtual addresses to guest physical addresses to host physical addresses'2015 9,164,901'Maintaining processor resources during architectural events'2015 9,152,561'Maintaining processor resources during architectural events'2015 9,141,555'Synchronizing a translation lookaside buffer with an extended paging table'2015 9,141,454'Signaling software recoverable errors'2015 9,122,624'Synchronizing a translation lookaside buffer with an extended paging table'2015 9,116,869'Posting interrupts to virtual processors'2015 9,086,958'Maintaining processor resources during architectural events'2015 8,997,099'Virtualization event processing in a layered virtualization architecture'2015 8,949,571'Synchronizing a translation lookaside buffer with an extended paging table'2015 8,938,606'System, apparatus, and method for segment register read and write regardless of privilege level'2015 8,938,737'Delivering interrupts directly to a virtual processor'2015 8,910,158'Virtualizing interrupt priority and delivery'2014 8,843,727'Performance enhancement of address translation using translation tables covering large address spaces'2014 8,843,683'Posting interrupts to virtual processors'2014 8,813,077'Virtualization event processing in a layered virtualization architecture'2014 8,806,172'Maintaining processor resources during architectural evens'2014 8,788,790'Maintaining processor resources during architectural events'2014 8,751,752'Invalidating translation lookaside buffer entries in a virtual machine system'2014 8,677,163'Context state management for processor feature sets'2014 8,645,665'Virtualizing physical memory in a virtual machine system utilizing multilevel translation table base registers to map guest virtual addresses to guest physical addresses then to host physical addresses'2014 8,635,415'Managing and implementing metadata in central processing unit using register extensions'2014 8,631,261'Context state management for processor feature sets'2014 8,607,228'Virtualizing performance counters'2013 8,601,233'Synchronizing a translation lookaside buffer with an extended paging table'2013 8,566,492'Posting interrupts to virtual processors'2013 8,561,068'Optimizing processor-managed resources based on the behavior of a virtual machine monitor'2013 8,543,793'Maintaining processor resources during architectural events'2013 8,543,772'Invalidating translation lookaside buffer entries in a virtual machine (VM) system'2013 8,533,428'Translating a guest virtual address to a host physical address as guest software executes on a virtual machine'2013 8,447,962'Gathering and scattering multiple data elements'2013 8,312,452'Method and apparatus for a guest to access a privileged register'2012 8,296,546'Synchronizing a translation lookaside buffer with an extended paging table'2012 8,291,410'Controlling virtual machines based on activity state'2012 8,286,162'Delivering interrupts directly to a virtual processor'2012 8,271,978'Virtualization event processing in a layered virtualization architecture'2012 8,230,203'Detecting spin loops in a virtual machine environment'2012 8,151,264'Injecting virtualization events in a layered virtualization architecture'2012 8,146,078'Timer offsetting mechanism in a virtual machine environment'2012 8,099,581'Synchronizing a translation lookaside buffer with an extended paging table'2012 8,079,034'Optimizing processor-managed resources based on the behavior of a virtual machine monitor'2011 7,984,203'Address window support for direct memory access translation'2011 7,975,267'Virtual interrupt processing in a layered virtualization architecture'2011 7,921,293'Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment'2011 7,904,694'Maintaining processor resources during architectural events'2011 7,899,972'Maintaining processor resources during architectural events'2011 7,900,204'Interrupt processing in a layered virtualization architecture'2011 7,886,126'Extended paging tables to map guest physical memory addresses from virtual memory page tables to host physical memory addresses in a virtual machine system'2011 7,865,670'Invalidating translation lookaside buffer entries in a virtual machine (VM) system'2011 7,861,245'Method and apparatus for facilitating recognition of an open event window during operation of guest software in a virtual machine environment'2010 7,840,962'System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time'2010 7,818,808'Processor mode for limiting the operation of guest software running on a virtual machine supported by a virtual machine monitor'2010 7,802,250'Support for transitioning to a virtual machine monitor based upon the privilege level of guest software'2010 7,793,286'Methods and systems to manage machine state in virtual machine operations'2010 7,757,231'System and method to deprivilege components of a virtual machine monitor'2010 7,620,949'Method and apparatus for facilitating recognition of an open event window during operation of guest software in a virtual machine environment'2009 7,581,219'Transitioning between virtual machine monitor domains in a virtual machine environment'2009 7,562,179'Maintaining processor resources during architectural events'2009 7,555,628'Synchronizing a translation lookaside buffer to an extended paging table'2009 7,506,121'Method and apparatus for a guest to access a memory mapped device'2009 7,467,381'Resource partitioning and direct access utilizing hardware support for virtualization'2008 7,444,493'Address translation for input/output devices using hierarchical translation tables'2008 7,424,709'Use of multiple virtual machine monitors to handle privileged events'2008 7,370,160'Virtualizing memory type'2008 7,356,735'Providing support for single stepping a virtual machine in a virtual machine environment'2008 7,340,582'Fault processing for direct memory access address translation'2008 7,334,107'Caching support for direct memory access address translation'2008 7,318,141'Methods and systems to control virtual machines'2008 7,313,669'Virtual translation lookaside buffer'2007 7,308,576'Authenticated code module'2007 7,305,592'Support for nested fault in a virtual machine environment'2007 7,302,511'Chipset support for managing hardware interrupts in a virtual machine system'2007 7,296,267'System and method for binding virtual machines to hardware contexts'2007 7,287,197'Vectoring an interrupt or exception upon resuming operation of a virtual machine'2007 7,272,831'Method and apparatus for constructing host processor soft devices independent of the host processor operating system'2007 7,237,051'Mechanism to control hardware interrupt acknowledgement in a virtual machine system'2007 7,225,441'Mechanism for providing power management through virtualization'2007 7,222,203'Interrupt redirection for virtual partitioning'2007 7,191,440'Tracking operating system process and thread execution and virtual machine execution in hardware or in a virtual machine monitor'2007 7,177,967'Chipset support for managing hardware interrupts in a virtual machine system'2007 7,127,548'Control register access virtualization performance improvement in the virtual-machine architecture'2006 7,124,273'Method and apparatus for translating guest physical addresses in a virtual machine environment'2006 7,124,327'Control over faults occurring during the operation of guest software in the virtual-machine architecture'2006 7,073,042'Reclaiming existing fields in address translation data structures to extend control over memory accesses'2006 7,035,963'Method for resolving address space conflicts between a virtual machine monitor and a guest operating system'2006 7,024,555'Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment'2006 7,020,738'Method for resolving address space conflicts between a virtual machine monitor and a guest operating system'2006 6,996,748'Handling faults associated with operation of guest software in the virtual-machine architecture'2006 6,907,600'Virtual translation lookaside buffer'2005 6,574,219'Passive message ordering on a decentralized ring'2003 6,377,582'Decentralized ring arbitration for multiprocessor computer systems'2002 6,112,283'Out-of-order snooping for multiprocessor computer systems'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2021Patents assigned to INTEL CORP (164)· patent assignee history

2000–2021Based in Portland, OR, US· patent location history

2011–2019Patents assigned to NEIGER GILBERT (39)· patent assignee history

2011–2019Patents assigned to ANDERSON ANDREW V (22)· patent assignee history

2011–2017Patents assigned to BENNETT STEVEN M (19)· patent assignee history

2011–2017Patents assigned to RODGERS DION (14)· patent assignee history

2012–2021Based in Hillsboro, OR, US· patent location history

2013Based in Portand, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	164	2000–2021
NEIGER GILBERTself	39	2011–2019
ANDERSON ANDREW V	22	2011–2019
BENNETT STEVEN M	19	2011–2017
RODGERS DION	14	2011–2017

Locations

Location	Patents	Span
Portland, OR, US	125	2000–2021
Hillsboro, OR, US	40	2012–2021
Portand, OR, US	1	2013