Inventor
Yasunobu Kodaira
Inventor
Tokyo, JP
Overview
Patents· 5 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests25%
H10BElectronic memory devices8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
PatentTitleYear
6,046,484'Gate structure of semiconductor memory'20005,238,873'Method for manufacturing semiconductor device having a metallic silicide layer'19935,213,988'Method of manufacturing bipolar transistor with self-aligned base regions'19935,126,278'Method of manufacturing bipolar transistor by implanting intrinsic impurities'19925,096,843'Method of manufacturing a bipolar CMOS device'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2000Patents assigned to TOSHIBA KK (5)· patent assignee history
1992–1993Based in Tokyo, JP· patent location history
2000Based in Kanagawa, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOSHIBA KK | 5 | 1992–2000 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 4 | 1992–1993 |
| Kanagawa, JP | 1 | 2000 |