Inventor
Fanling H. Yang
Inventor
Beaverton, OR, US
Overview
Patents· 7 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices55%
H01LSemiconductor devices27%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
PatentTitleYear
9,673,316'Vertical semiconductor device having frontside interconnections'20179,450,074'LDMOS with field plate connected to gate'20169,209,091'Integrated monolithic galvanic isolator'20157,026,666'Self-aligned NPN transistor with raised extrinsic base'20066,767,798'Method of forming self-aligned NPN transistor with raised extrinsic base'20046,686,250'Method of forming self-aligned bipolar transistor'20046,303,413'Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2017Patents assigned to MAXIM INTEGRATED PRODUCTS (7)· patent assignee history
2001–2017Based in Beaverton, OR, US· patent location history
2015–2016Patents assigned to BOUCHE GUILLAUME (2)· patent assignee history
2015–2016Patents assigned to UPPILI SUDARSAN (2)· patent assignee history
2015–2016Patents assigned to YANG FANLING HSU (2)· patent assignee history
2015Patents assigned to BLAIR CHRISTOPHER S (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MAXIM INTEGRATED PRODUCTS | 7 | 2001–2017 |
| BOUCHE GUILLAUME | 2 | 2015–2016 |
| UPPILI SUDARSAN | 2 | 2015–2016 |
| YANG FANLING HSUself | 2 | 2015–2016 |
| BLAIR CHRISTOPHER S | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 7 | 2001–2017 |