Inventor
Hai Cong
Inventor
Singapore, SG
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10DInorganic electric semiconductor devices15%
H10BElectronic memory devices11%
H10NElectric solid-state devices not otherwise provided for8%
F28DHeat-exchange apparatus, not provided for in another subclass, in which the heat-exchange media do not come into direct contact2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
G06FElectric digital data processing2%
H01JElectric discharge tubes or discharge lamps2%
PatentTitleYear
10,608,046Integrated two-terminal device with logic device for embedded application202010,510,825Metal-insulator-metal capacitor with improved time-dependent dielectric breakdown201910,461,247Integrated magnetic random access memory with logic device having low-K interconnects201910,446,607Integrated two-terminal device with logic device for embedded application201910,115,625Methods for removal of hard mask201810,103,097CD control20189,972,775Integrated magnetic random access memory with logic device having low-k interconnects20189,805,971'Method of forming a via contact'20179,564,575'Dual encapsulation integration scheme for fabricating integrated circuits with magnetic random access memory structures'20179,520,299'Etch bias control'20169,437,550'TSV without zero alignment marks'20169,230,886'Method for forming through silicon via with wafer backside protection'20168,987,134'Reliable interconnect for semiconductor device'20158,940,637'Method for forming through silicon via with wafer backside protection'20158,836,139'CD control'20148,828,858'Spacer profile engineering using films with continuously increased etch rate from inner to outer surface'20148,737,061'Heat dissipating apparatus'20148,546,873'Integrated circuit and method of fabrication thereof'20138,518,775'Integration of eNVM, RMG, and HKMG modules'20138,492,236'Step-like spacer profile'20138,394,724'Processing with reduced line end shortening ratio'20138,293,545'Critical dimension for trench and vias'20128,058,123'Integrated circuit and method of fabrication thereof'20117,960,283'Method for reducing silicide defects in integrated circuits'20117,892,900'Integrated circuit system employing sacrificial spacers'20117,879,732'Thin film etching method and semiconductor device fabrication using same'20117,745,320'Method for reducing silicide defects in integrated circuits'20107,247,555'Method to control dual damascene trench etch profile and trench depth uniformity'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2011Patents assigned to CHARTERED SEMICONDUCTOR MFG (4)· patent assignee history
2007–2020Based in Singapore, SG· patent location history
2011–2020Patents assigned to GLOBALFOUNDRIES SG PTE LTD (23)· patent assignee history
2011–2015Patents assigned to CONG HAI (8)· patent assignee history
2011–2013Patents assigned to HSIA LIANG CHOO (3)· patent assignee history
2013–2015Patents assigned to ZOU ZHENG (4)· patent assignee history
2014Based in Jiangsu, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES SG PTE LTD | 23 | 2011–2020 |
| CONG HAIself | 8 | 2011–2015 |
| CHARTERED SEMICONDUCTOR MFG | 4 | 2007–2011 |
| ZOU ZHENG | 4 | 2013–2015 |
| HSIA LIANG CHOO | 3 | 2011–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Singapore, SG | 27 | 2007–2020 |
| Jiangsu, CN | 1 | 2014 |