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Inventor

Vivian W. Ryan

Inventor
Berne, NY, US

Overview

48→
Patents
1989–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 48 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1045%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H01LSemiconductor devices10%
G01RMeasuring electric variables6%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
Y10TTechnical subjects covered by former us classification2%
C03CChemical composition of glasses, glazes or vitreous enamels1%
C23CCoating metallic material1%
G05DSystems for controlling or regulating non-electric variables1%
PatentTitleYear
10,755,827Radiation shield202010,291,231Superconducting device with dummy elements20199,297,775'Combinatorial screening of metallic diffusion barriers'20169,269,615'Multi-layer barrier layer for interconnect structure'20169,209,135'Method for reducing wettability of interconnect material at corner interface and device incorporating same'20159,076,792'Multi-layer barrier layer stacks for interconnect structures'20159,059,255'Methods of forming non-continuous conductive layers for conductive structures on an integrated circuit product'20159,021,894'Detecting anomalous weak BEOL sites in a metallization system'20158,950,269'Detecting anomalous stiff pillar bumps formed above a metallization system'20158,928,146'Bond pad configurations for controlling semiconductor chip package interactions'20158,877,633'Methods of forming a barrier system containing an alloy of metals introduced into the barrier system, and an integrated circuit product containing such a barrier system'20148,829,675'Repairing anomalous stiff pillar bumps'20148,772,158'Multi-layer barrier layer stacks for interconnect structures'20148,728,931'Multi-layer barrier layer for interconnect structure'20148,722,534'Method for reducing wettability of interconnect material at corner interface and device incorporating same'20148,680,681'Bond pad configurations for controlling semiconductor chip package interactions'20148,664,759'Integrated circuit with heat conducting structures for localized thermal control'20148,623,758'Subtractive metal multi-layer barrier layer for interconnect structure'20148,623,754'Repairing anomalous stiff pillar bumps'20148,441,131'Strain-compensating fill patterns for controlling semiconductor chip package interactions'20137,973,544'Thermal monitoring and management of integrated circuits'20117,800,879'On-chip sensor array for temperature management in integrated circuits'20107,745,927'Heat sink formed of multiple metal layers on backside of integrated circuit die'20107,705,473'Methods and apparatus for determining pad height for a wire-bonding operation in an integrated circuit'20107,573,097'Lateral double diffused MOS transistors'20097,504,728'Integrated circuit having bond pad with improved thermal and mechanical properties'20097,429,502'Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink'20087,339,274'Metallization performance in electronic devices'20087,327,029'Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink'20087,157,365'Semiconductor device having a dummy conductive via and a method of manufacture therefor'20077,056,819'Methods and apparatus for determining pad height for a wire-bonding operation in an integrated circuit'20066,919,228'Methods and apparatus for the detection of damaged regions on dielectric film or other portions of a die'20056,833,557'Integrated circuit and a method of manufacturing an integrated circuit'20046,747,445'Stress migration test structure and method therefor'20046,683,465'Integrated circuit having stress migration test structure and method therefor'20046,621,280'Method of testing an integrated circuit'20036,620,720'Interconnections to copper IC\'s'20036,410,435'Process for fabricating copper interconnect for ULSI integrated circuits'20026,207,547'Bond pad design for integrated circuits'20016,187,658'Bond pad for a flip chip package, and method of forming the same'20016,087,732'Bond pad for a flip-chip package'20006,004,827'Integrated circuit processing'19995,986,343'Bond pad design for integrated circuits'19995,930,587'Stress migration evaluation method'19995,599,737'Conductive runner fabrication'19975,243,221'Aluminum metallization doped with iron and copper to prevent electromigration'19934,975,389'Aluminum metallization for semiconductor devices'19904,826,709'Devices involving silicon glasses'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989–1993Based in Nutley, NJ, US· patent location history
1997–2001Patents assigned to LUCENT TECHNOLOGIES INC (7)· patent assignee history
1997–2004Based in Washington, NJ, US· patent location history
2002–2014Based in Hampton, NJ, US· patent location history
2003–2011Patents assigned to AGERE SYSTEMS INC (17)· patent assignee history
2013–2016Patents assigned to GLOBALFOUNDRIES INC (16)· patent assignee history
2013–2016Patents assigned to RYAN VIVIAN W (8)· patent assignee history
2013–2016Based in Berne, NY, US· patent location history
2014–2015Patents assigned to BREUER DIRK (3)· patent assignee history
2019–2020Based in Severn, MD, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
AGERE SYSTEMS INC172003–2011
GLOBALFOUNDRIES INC162013–2016
RYAN VIVIAN Wself82013–2016
LUCENT TECHNOLOGIES INC71997–2001
BREUER DIRK32014–2015
Locations
LocationPatentsSpan
Berne, New York, US172013–2016
Hampton, New Jersey, US132002–2014
Washington, New Jersey, US121997–2004
Nutley, New Jersey, US31989–1993
Severn, Maryland, US22019–2020