Inventor

Cheng-Hsien Wu

Inventor
Hsinchu, TW

Overview

108→
Patents
2012–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 108 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices31%
H01LSemiconductor devices27%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
B82YSpecific uses or applications of nanostructures3%
B29CShaping or joining of plastics1%
C12NMicroorganisms or enzymes1%
C12PFermentation or enzyme-using processes to synthesise a desired chemical compound or composition or to separate optical isomers from a racemic mixture1%
G02BOptical elements, systems or apparatus1%
C30BSingle-crystal growth0%
PatentTitleYear
11,128,130Protection circuit with bidirectional surge protection202110,879,065III-V compound semiconductors in isolation regions and method forming same202010,879,080Methods for forming polycrystalline channel on dielectric films with controlled grain boundaries202010,797,162FinFET device having a channel defined in a diamond-like shape semiconductor structure202010,770,592Multi-gate semiconductor device and method for forming the same202010,727,351Semiconductor structures and methods with high mobility and high energy bandgap materials202010,727,344Method of manufacturing a semiconductor device with multilayered channel structure202010,700,206Semiconductor device and manufacturing method thereof202010,665,674FinFET semiconductor device with germanium diffusion over silicon fins202010,622,261FinFET devices with unique shape and the fabrication thereof202010,522,625Multi-gate device and method of fabrication thereof201910,522,345Lattice-mismatched semiconductor substrates with defect reduction201910,522,694Methods of manufacturing semiconductor device201910,516,056Semiconductor device and manufacturing method thereof201910,516,032Method of manufacturing a semiconductor device201910,510,754Complimentary metal-oxide-semiconductor (CMOS) with low contact resistivity and method of forming same201910,504,993FinFET semiconductor device with germanium diffusion over silicon fins201910,504,796Semiconductor device and method for manufacturing the same201910,431,696Structure and formation method of semiconductor device structure with nanowire201910,355,133Method for forming a semiconductor device including a stacked wire structure201910,326,021Source/drain profile for FinFeT201910,304,826Complimentary metal-oxide-semiconductor (CMOS) with low contact resistivity and method of forming same201910,283,414Isolation manufacturing method for semiconductor structures201910,269,969Semiconductor structures and methods with high mobility and high energy bandgap materials201910,269,965Multi-gate semiconductor device and method for forming the same201910,269,934Method for manufacturing tunnel field effect transistor201910,263,091Multiple gate field effect transistors having oxygen-scavenged gate stack201910,263,097Method of semiconductor arrangement formation201910,170,375FinFET devices with unique fin shape and the fabrication thereof201910,170,374Semiconductor device and method for manufacturing the same201910,164,023FinFETs with strained well regions201810,163,628Lattice-mismatched semiconductor substrates with defect reduction201810,164,062FinFET device having a channel defined in a diamond-like shape semiconductor structure201810,158,015FinFETs with strained well regions201810,147,819Semiconductor device and manufacturing method thereof201810,134,843Multi-gate device and method of fabrication thereof201810,115,826Semiconductor structure and the manufacturing method thereof201810,096,710Method of forming strained structures of semiconductor devices201810,084,069Apparatus and method for FinFETs201810,062,782Method of manufacturing a semiconductor device with multilayered channel structure201810,026,641Isolation structure of semiconductor device201810,002,969Semiconductor device and manufacturing method thereof20189,985,131Source/drain profile for FinFET20189,922,828'Apparatus and method for FinFETs'20189,873,900RNA-mediated gene assembly from DNA oligonucleotides20189,870,920'Growing III-V compound semiconductors from trenches filled with intermediate layers'20189,859,380'FinFETs with strained well regions'20189,786,543'Isolation structure of semiconductor device'20179,780,174'Methods for forming semiconductor regions in trenches'20179,773,889'Method of semiconductor arrangement formation'20179,748,143'FinFETs with strained well regions'20179,748,388'Method of forming strained structures of semiconductor devices'20179,735,274'Semiconductor device including a stacked wire structure'20179,722,051'Apparatus and method for FinFETs'20179,677,067'Compositions and methods for synthetic gene assembly'20179,660,033'Multi-gate device and method of fabrication thereof'20179,659,780'Multiple gate field-effect transistors having oxygen-scavenged gate stack'20179,627,540'Semiconductor device and manufacturing method thereof'20179,601,342'FinFETs with strained well regions'20179,601,594'Semiconductor device with enhanced strain'20179,595,614'Semiconductor structures and methods with high mobility and high energy bandgap materials'20179,583,379'Inverted trapezoidal recess for epitaxial growth'20179,583,399'Semiconductor device and manufacturing method thereof'20179,564,489'Multiple gate field-effect transistors having oxygen-scavenged gate stack'20179,559,099'Apparatus and method for FinFETs'20179,553,012'Semiconductor structure and the manufacturing method thereof'20179,553,149'Semiconductor device with a strained region and method of making'20179,548,303'FinFET devices with unique fin shape and the fabrication thereof'20179,530,776'FinFET semiconductor device with germanium diffusion over silicon fins'20169,502,539'FINFET device having a channel defined in a diamond-like shape semiconductor structure'20169,455,320'FinFETs with strained well regions'20169,450,098'FinFET having superlattice stressor'20169,390,982'CMOS devices with reduced leakage and methods of forming the same'20169,337,304'Method of making semiconductor device'20169,279,932'LGF roll-to-roll manufacturing method and structure thereof'20169,276,117'Structure and method and FinFET device'20169,246,004'Strained structures of semiconductor devices'20169,233,496'Adjustment mechanism of mold system having electrically adjusting and positioning functions'20169,224,734'CMOS devices with reduced leakage and methods of forming the same'20159,209,066'Isolation structure of semiconductor device'20159,209,023'Growing III-V compound semiconductors from trenches filled with intermediate layers'20159,196,709'Methods for forming semiconductor regions in trenches'20159,184,050'Inverted trapezoidal recess for epitaxial growth'20159,159,824'FinFETs with strained well regions'20159,153,582'Apparatus and method for FinFETs'20159,123,633'Methods for forming semiconductor regions in trenches'20159,105,654'Source/drain profile for FinFET'20159,087,902'FinFETs with strained well regions'20159,076,819'Contact structure of semiconductor device'20158,994,002'FinFET having superlattice stressor'20158,969,156'Semiconductor structures and methods with high mobility and high energy bandgap materials'20158,878,302'Semiconductor device having SiGe substrate, interfacial layer and high K dielectric layer'20148,841,701'FinFET device having a channel defined in a diamond-like shape semiconductor structure'20148,836,016'Semiconductor structures and methods with high mobility and high energy bandgap materials'20148,815,712'Method for epitaxial re-growth of semiconductor region'20148,786,019'CMOS FinFET device'20148,759,203'Growing III-V compound semiconductors from trenches filled with intermediate layers'20148,742,509'Apparatus and method for FinFETs'20148,721,148'LGF plate-to-plate manufacturing method and structure thereof'20148,716,765'Contact structure of semiconductor device'20148,629,012'Method for forming antimony-based FETs monolithically'20148,618,556'FinFET design and method of fabricating same'20138,609,517'MOCVD for growing III-V compound semiconductors on silicon substrates'20138,486,770'Method of forming CMOS FinFET device'20138,426,890'Semiconductor device and manufacturing method with improved epitaxial quality of III-V compound on silicon surfaces'20138,253,167'Method for forming antimony-based FETs monolithically'20128,242,540'Epitaxial growth of III-V compound semiconductors on silicon surfaces'20128,183,134'Semiconductor device and manufacturing method with improved epitaxial quality of III-V compound on silicon surfaces'2012

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2012–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (33)· patent assignee history
2012–2017Patents assigned to WU CHENG-HSIEN (22)· patent assignee history
2012–2017Patents assigned to KO CHIH-HSIN (19)· patent assignee history
2012–2017Patents assigned to WANN CLEMENT HSINGJEN (17)· patent assignee history
2012–2015Based in Taipei, TW· patent location history
2013–2020Based in Hsinchu, TW· patent location history
2014–2016Based in Kaohsiung, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (69)· patent assignee history
2018Based in Madison, WI, US· patent location history
2021Based in Shanghai, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG CO LTD692016–2020
TAIWAN SEMICONDUCTOR MFG332012–2016
WU CHENG-HSIENself222012–2017
KO CHIH-HSIN192012–2017
WANN CLEMENT HSINGJEN172012–2017
Locations
LocationPatentsSpan
Hsinchu, TW942013–2020
Taipei, TW82012–2015
Kaohsiung, TW32014–2016
Shanghai, CN12021
Madison, WI, US12018