Inventor

Michael R. Butts

Inventor

Portland, OR, US

Overview

1991–2014

Patent span

Physics

Primary field (CPC G)

Patents· 52 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary

H03KPulse technique42%

G06FElectric digital data processing35%

G11CStatic stores8%

G01RMeasuring electric variables7%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%

G05BControl or regulating systems in general1%

H04LTransmission of digital information, e.g. telegraphic communication1%

PatentTitleYear

8,810,277'Non-sequentially configurable IC'2014 8,638,119'Configurable circuits, IC\'s, and systems'2014 8,305,110'Non-sequentially configurable IC'2012 8,193,830'Configurable circuits, IC\'s, and systems'2012 8,103,866'System for reconfiguring a processor array'2012 7,948,266'Non-sequentially configurable IC'2011 7,872,496'Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits'2011 7,801,033'System of virtual data channels in an integrated circuit'2010 7,792,933'System and method for performing design verification'2010 7,739,097'Emulation system with time-multiplexed interconnect'2010 7,667,486'Non-sequentially configurable IC'2010 7,616,027'Configurable circuits, IC\'s and systems'2009 7,532,032'Configurable circuits, IC\'s, and systems'2009 7,425,841'Configurable circuits, IC\'s, and systems'2008 7,408,382'Configurable circuits, IC\'s, and systems'2008 7,260,794'Logic multiprocessor for FPGA implementation'2007 7,193,440'Configurable circuits, IC\'s, and systems'2007 7,167,025'Non-sequentially configurable IC'2007 7,157,933'Configurable circuits, IC\'s, and systems'2007 7,109,752'Configurable circuits, IC\'s, and systems'2006 6,882,176'High-performance programmable logic architecture'2005 6,810,373'Method and apparatus for modeling using a hardware-software co-verification environment'2004 6,732,068'Memory circuit for use in hardware emulation system'2004 6,625,793'Optimized emulation and prototyping architecture'2003 6,570,404'High-performance programmable logic architecture'2003 6,539,535'Programmable logic device having integrated probing structures'2003 6,377,912'Emulation system with time-multiplexed interconnect'2002 6,353,552'PLD with on-chip memory having a shadow register'2002 6,317,367'FPGA with on-chip multiport memory'2001 6,289,494'Optimized emulation and prototyping architecture'2001 6,285,211'I/O buffer circuit with pin multiplexing'2001 6,259,588'Input/output buffer with overcurrent protection circuit'2001 6,219,284'Programmable logic device with multi-port memory'2001 6,184,707'Look-up table based logic element with complete permutability of the inputs to the secondary signals'2001 6,151,258'Programmable logic device with multi-port memory'2000 6,034,857'Input/output buffer with overcurrent protection circuit'2000 6,020,760'I/O buffer circuit with pin multiplexing'2000 6,011,730'Programmable logic device with multi-port memory'2000 6,011,744'Programmable logic device with multi-port memory'2000 6,002,861'Method for performing simulation using a hardware emulation system'1999 5,960,191'Emulation system with time-multiplexed interconnect'1999 5,870,410'Diagnostic interface system for programmable logic system development'1999 5,821,773'Look-up table based logic element with complete permutability of the inputs to the secondary signals'1998 5,812,414'Method for performing simulation using a hardware logic emulation system'1998 5,796,623'Apparatus and method for performing computations with electrically reconfigurable logic devices'1998 5,734,581'Method for implementing tri-state nets in a logic emulation system'1998 5,661,662'Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation'1997 5,657,241'Routing methods for use in a logic emulation system'1997 5,612,891'Hardware logic emulation system with memory capability'1997 5,452,231'Hierarchically connected reconfigurable logic assembly'1995 5,448,496'Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system'1995 5,036,473'Method of using electronically reconfigurable logic circuits'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991–2014Based in Portland, OR, US· patent location history

1995–2010Patents assigned to QUICKTURN DESIGN SYSTEMS INC (29)· patent assignee history

1998–2003Patents assigned to ALTERA CORP (14)· patent assignee history

1998–2012Based in Beaverton, OR, US· patent location history

2006–2014Patents assigned to BUTTS MICHAEL (8)· patent assignee history

2006–2014Patents assigned to HUTCHINGS BRAD L (8)· patent assignee history

2008–2014Patents assigned to TABULA INC (10)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
QUICKTURN DESIGN SYSTEMS INC	29	1995–2010
ALTERA CORP	14	1998–2003
TABULA INC	10	2008–2014
BUTTS MICHAELself	8	2006–2014
HUTCHINGS BRAD L	8	2006–2014

Locations

Location	Patents	Span
Portland, OR, US	46	1991–2014
Beaverton, OR, US	6	1998–2012