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Inventor

Vyacheslav Zavadsky

Inventor
Ottawa, CA

Overview

18→
Patents
2007–2021
Patent span
Physics
Primary field (CPC G)

Patents· 18 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing31%
G06TImage data processing or generation, in general21%
G01RMeasuring electric variables14%
A63BApparatus for physical training, gymnastics, swimming, climbing, or fencing7%
A63FCard, board, or roulette games7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes3%
G06VImage or video recognition or understanding3%
G07FCoin-freed or like apparatus3%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
11,088,840Trusted terminal platform20218,701,058'Integrated circuit analysis systems and methods'20148,606,041'Method of local tracing of connectivity and schematic representations produced therefrom'20138,347,262'Method of deriving an integrated circuit schematic diagram'20138,287,434'Method and apparatus for facilitating strength training'20128,219,940'Method and apparatus for removing dummy features from a data structure'20128,051,395'Method of labelling swappable pins for integrated circuit pattern matching'20117,967,728'Wireless game controller for strength training and physiotherapy'20117,899,640'Integrated circuit characterisation system and method'20117,886,258'Method and apparatus for removing dummy features from a data structure'20117,873,203'Method of design analysis of existing integrated circuits'20117,765,517'Method and apparatus for removing dummy features from a data structure'20107,751,643'Method and apparatus for removing uneven brightness in an image'20107,693,348'Method of registering and aligning multiple images'20107,643,665'Method of design analysis of existing integrated circuits'20107,580,557'Method of design analysis of existing integrated circuits'20097,278,121'Method and apparatus for reducing redundant data in a layout data structure'20077,207,018'Method and apparatus for locating short circuit faults in an integrated circuit layout'2007

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2014Patents assigned to SEMICONDUCTOR INSIGHTS INC (15)· patent assignee history
2007–2014Based in Ottawa, CA· patent location history
2011–2013Patents assigned to ZAVADSKY VYACHESLAV (4)· patent assignee history
2011–2012Patents assigned to SHERSTYUK MYKOLA (2)· patent assignee history
2012–2014Patents assigned to KEYES EDWARD (4)· patent assignee history
2013–2014Patents assigned to ZAVADSKY VYACHESLAV L (2)· patent assignee history
2021Based in Prague, CZ· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SEMICONDUCTOR INSIGHTS INC152007–2014
KEYES EDWARD42012–2014
ZAVADSKY VYACHESLAVself42011–2013
SHERSTYUK MYKOLA22011–2012
ZAVADSKY VYACHESLAV Lself22013–2014
Locations
LocationPatentsSpan
Ottawa, CA172007–2014
Prague, CZ12021