Inventor
Bryan L. Jackson
Inventor
Fremont, CA, US
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Nprimary
G06NComputing arrangements based on specific computational models42%
G06FElectric digital data processing18%
H01LSemiconductor devices5%
H10BElectronic memory devices5%
H10DInorganic electric semiconductor devices5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
A01HNew plants or non-transgenic processes for obtaining them4%
G01RMeasuring electric variables4%
H04LTransmission of digital information, e.g. telegraphic communication4%
H04WWireless communication networks4%
PatentTitleYear
11,049,001Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network202110,990,872Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency202110,984,307Peripheral device interconnections for neurosynaptic systems202110,929,747Dual deterministic and stochastic neurosynaptic core circuit202110,832,151Implementing stochastic networks using magnetic tunnel junctions202010,785,745Scaling multi-core neurosynaptic networks across chip boundaries202010,769,519Converting digital numeric data to spike event data202010,755,165Converting spike event data to digital numeric data202010,740,282Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array202010,678,741Coupling parallel event-driven computation with serial computation202010,650,301Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation202010,454,759Yield tolerance in a neurosynaptic system201910,410,109Peripheral device interconnections for neurosynaptic systems201910,102,474Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network20189,992,057Yield tolerance in a neurosynaptic system20189,984,324Dual deterministic and stochastic neurosynaptic core circuit20189,940,302Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array20189,924,490'Scaling multi-core neurosynaptic networks across chip boundaries'20189,886,662'Converting spike event data to digital numeric data'20189,881,252'Converting digital numeric data to spike event data'20189,852,006Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits20179,797,946'Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs'20179,792,251'Array of processor core circuits with reversible tiers'20179,747,545'Self-timed, event-driven neurosynaptic core controller'20179,588,937'Array of processor core circuits with reversible tiers'20179,558,443'Dual deterministic and stochastic neurosynaptic core circuit'20179,466,030'Implementing stochastic networks using magnetic tunnel junctions'20169,390,368'Coupling parallel event-driven computation with serial computation'20169,368,489'Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array'20169,244,124'Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs'20168,527,438'Producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array'2013PP022158'Cuphea plant named ‘Southern Border’'20117,446,929'Photonic device including at least one electromagnetic resonator operably coupled to a state-change material'2008PP014834'Erigeron plant named Spindrift'20046,085,460'System for holding plant containers'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004Based in Braeside, Victoria, AU· patent location history
2008Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (1)· patent assignee history
2008Based in Oakland, CA, US· patent location history
2011Patents assigned to JACKSON BRYAN (1)· patent assignee history
2011Based in Dromana, AU· patent location history
2013–2021Patents assigned to IBM (31)· patent assignee history
2013Patents assigned to JACKSON BRYAN LAWRENCE (1)· patent assignee history
2013Based in San Jose, CA, US· patent location history
2016Patents assigned to JACKSON BRYAN L (1)· patent assignee history
2016–2021Based in Fremont, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 31 | 2013–2021 |
| HEWLETT PACKARD DEVELOPMENT CO | 1 | 2008 |
| JACKSON BRYANself | 1 | 2011 |
| JACKSON BRYAN Lself | 1 | 2016 |
| JACKSON BRYAN LAWRENCEself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 30 | 2016–2021 |
| San Jose, California, US | 1 | 2013 |
| Dromana, AU | 1 | 2011 |
| Oakland, California, US | 1 | 2008 |
| Braeside, Victoria, AU | 1 | 2004 |