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Inventor

Tom Zhong

Inventor
Saratoga, CA, US

Overview

44→
Patents
2001–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 44 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Nprimary
H10NElectric solid-state devices not otherwise provided for25%
H10BElectronic memory devices16%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices11%
H01LSemiconductor devices11%
G11CStatic stores7%
B05DProcesses for applying fluent materials to surfaces, in general4%
B05CApparatus for applying fluent materials to surfaces, in general3%
G11BInformation storage based on relative movement between record carrier and transducer2%
H01FMagnets2%
PatentTitleYear
10,868,244Multiple hard mask patterning to fabricate 20nm and below MRAM devices202010,854,809STT-MRAM heat sink and magnetic shield structure design for more robust read/write performance202010,831,104Critical dimension (CD) uniformity of photoresist island patterns using alternating phase shifting mask202010,520,818Critical dimension (CD) uniformity of photoresist island patterns using alternating phase shifting mask201910,475,987Method for fabricating a magnetic tunneling junction (MTJ) structure201910,446,741Multiple hard mask patterning to fabricate 20nm and below MRAM devices201910,103,322Method to remove sidewall damage after MTJ etching201810,069,064Memory structure having a magnetic tunnel junction (MTJ) self-aligned to a T-shaped bottom electrode, and method of manufacturing the same20189,972,777MTJ device process/integration method with pre-patterned seed layer20189,880,473'Surface treatment method for dielectric anti-reflective coating (DARC) to shrink photoresist critical dimension (CD)'20189,608,200'Hybrid metallic hard mask stack for MTJ etching'20179,343,463'Method of high density memory fabrication'20168,969,982'Bottom electrode for MRAM device'20158,933,542'Method to reduce magnetic film stress for better yield'20158,803,293'Method to reduce magnetic film stress for better yield'20148,772,051'Fabrication method for embedded magnetic memory'20148,722,543'Composite hard mask with upper sacrificial dielectric layer for the patterning and etching of nanometer size MRAM devices'20148,636,911'Process for MEMS scanning mirror with mass remove from mirror backside'20148,524,511'Method to connect a magnetic device to a CMOS transistor'20138,324,698'High density spin-transfer torque MRAM process'20128,273,666'Process to fabricate bottom electrode for MRAM device'20128,183,061'High density spin-transfer torque MRAM process'20128,133,745'Method of magnetic tunneling layer processes for spin-transfer torque MRAM'20128,105,948'Use of CMP to contact a MTJ structure without forming a via'20127,936,027'Method of MRAM fabrication with zero electrical shorting'20117,919,407'Method of high density field induced MRAM process'20117,884,433'High density spin-transfer torque MRAM process'20117,863,060'Method of double patterning and etching magnetic tunnel junction structures for spin-transfer torque MRAM devices'20117,838,436'Bottom electrode for MRAM device and method to fabricate it'20107,804,706'Bottom electrode mask design for ultra-thin interlayer dielectric approach in MRAM device fabrication'20107,508,700'Method of magnetic tunneling junction pattern layout for magnetic random access memory'20097,476,919'MRAM cell structure and method of fabrication'20097,122,386'Method of fabricating contact pad for magnetic random access memory'20067,045,368'MRAM cell structure and method of fabrication'20067,030,039'Method of uniformly coating a substrate'20067,018,943'Method of uniformly coating a substrate'20066,977,098'Method of uniformly coating a substrate'20056,911,091'Environment exchange control for material on a wafer surface'20056,844,027'Environment exchange control for material on a wafer surface'20056,780,461'Environment exchange control for material on a wafer surface'20046,662,466'Method for two dimensional adaptive process control of critical dimensions during spin coating process'20036,468,586'Environment exchange control for material on a wafer surface'20026,327,793'Method for two dimensional adaptive process control of critical dimensions during spin coating process'20016,254,936'Environment exchange control for material on a wafer surface'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2006Based in Santa Clara, CA, US· patent location history
2006–2014Patents assigned to MAGIC TECHNOLOGIES INC (14)· patent assignee history
2006–2015Based in Cupertino, CA, US· patent location history
2006–2009Based in Sunnyvale, CA, US· patent location history
2009–2016Patents assigned to HEADWAY TECHNOLOGIES INC (8)· patent assignee history
2010–2020Based in Saratoga, CA, US· patent location history
2012–2016Patents assigned to ZHONG TOM (11)· patent assignee history
2012–2016Patents assigned to TORNG CHYU-JIUH (8)· patent assignee history
2019–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MAGIC TECHNOLOGIES INC142006–2014
ZHONG TOMself112012–2016
HEADWAY TECHNOLOGIES INC82009–2016
TORNG CHYU-JIUH82012–2016
TAIWAN SEMICONDUCTOR MFG CO LTD62019–2020
Locations
LocationPatentsSpan
Saratoga, California, US272010–2020
Santa Clara, California, US102001–2006
Cupertino, California, US52006–2015
Sunnyvale, California, US22006–2009