Inventor
Nachiket R. Raravikar
Inventor
Gilbert, AZ, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
B82YSpecific uses or applications of nanostructures10%
H01LSemiconductor devices10%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
Y10TTechnical subjects covered by former us classification9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
C01BNon-metallic elements4%
H05KPrinted circuits4%
B05DProcesses for applying fluent materials to surfaces, in general3%
H01BCables3%
PatentTitleYear
11,062,970Heat spreader edge standoffs for managing bondline thickness in microelectronic packages202110,672,626Method and materials for warpage thermal and interconnect solutions202010,615,128Systems and methods for electromagnetic interference shielding202010,607,909Systems, methods, and apparatuses for implementing a thermal solution for 3D packaging202010,586,779LPS solder paste based low cost fine pitch pop interconnect solutions202010,515,914Sintered solder for fine pitch first-level interconnect (FLI) applications201910,461,007Semiconductor package with electromagnetic interference shielding201910,224,299Sintered solder for fine pitch first-level interconnect (FLI) applications201910,181,432Computing system with a thermal interface comprising magnetic particles201910,163,810Electromagnetic interference shielding for system-in-package technology20189,953,929Systems and methods for electromagnetic interference shielding20189,941,652Space transformer with perforated metallic plate for electrical die test20189,831,206LPS solder paste based low cost fine pitch pop interconnect solutions20179,795,038'Electronic package design that facilitates shipping the electronic package'20179,669,425'Thermally and electrically conductive structure, method of applying a carbon coating to same, and method of reducing a contact resistance of same'20179,607,964'Method and materials for warpage thermal and interconnect solutions'20179,458,283'Flexible underfill compositions for enhanced reliability'20169,214,420'Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same'20159,159,464'Thermally and electrically conductive structure comprising a carbon nanotube, a graphite sheet and a metal layer; and method of reducing a contact resistance of same'20159,068,067'Flexible underfill compositions for enhanced reliability'20159,028,142'Integrated microelectronic package temperature sensor'20158,916,981'Epoxy-amine underfill materials for semiconductor packages'20148,724,290'Nanolithographic method of manufacturing an embedded passive device for a microelectronic application, and microelectronic device containing same'20148,586,393'Stress sensor for in-situ measurement of package-induced stress in semiconductor devices'20138,569,108'Coating for a microelectronic device, treatment comprising same, and method of managing a thermal profile of a microelectronic die'20138,558,218'Methods of forming carbon nanotubes architectures and composites with high electrical and thermal conductivites and structures formed thereby'20138,530,890'Aligned nanotube bearing composite material'20138,409,665'Method for reducing contact resistance of a thermally and electrically conductive structure comprising carbon nanotube'20138,344,483'Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same'20138,287,996'Coating for a microelectronic device, treatment comprising same, and method of managing a thermal profile of a microelectronic die'20128,222,750'Aligned nanotube bearing composite material'20128,174,084'Stress sensor for in-situ measurement of package-induced stress in semiconductor devices'20128,158,968'Methods of forming carbon nanotubes architectures and composites with high electrical and thermal conductivities and structures formed thereby'20128,133,585'Thermally and electrically conductive structure comprising a carbon nanotube and a carbon coating, and method of reducing a contact resistance of same'20128,068,328'Nanolithographic method of manufacturing an embedded passive device for a microelectronic application, and microelectronic device containing same'20117,799,849'Method to fabricate self-healing material'20107,781,260'Methods of forming nano-coatings for improved adhesion between first level interconnects and epoxy under-fills in microelectronic packages and structures formed thereby'20107,713,858'Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same'20107,700,943'In-situ functionalization of carbon nanotubes'20107,666,768'Through-die metal vias with a dispersed phase of graphitic structures of carbon for reduced thermal expansion and increased electrical conductance'20107,618,679'Thermally and electrically conductive structure, method of applying a carbon coating to same, and method of reducing a contact resistance of same'20097,553,681'Carbon nanotube-based stress sensor'20097,534,648'Aligned nanotube bearing composite material'20097,465,605'In-situ functionalization of carbon nanotubes'20087,371,674'Nanostructure-based package interconnect'20086,782,154'Ultrafast all-optical switch using carbon nanotube polymer composites'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004Based in Troy, NY, US· patent location history
2008–2021Patents assigned to INTEL CORP (45)· patent assignee history
2008–2015Based in Chandler, AZ, US· patent location history
2009–2020Based in Gilbert, AZ, US· patent location history
2010Based in AZ, US· patent location history
2011–2017Patents assigned to RARAVIKAR NACHIKET R (11)· patent assignee history
2012–2015Patents assigned to RARAVIKAR NACHIKET (6)· patent assignee history
2012–2013Patents assigned to SUH DAEWOONG (3)· patent assignee history
2012–2015Patents assigned to XU DINGYING (3)· patent assignee history
2019–2021Based in Saratoga, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 45 | 2008–2021 |
| RARAVIKAR NACHIKET Rself | 11 | 2011–2017 |
| RARAVIKAR NACHIKETself | 6 | 2012–2015 |
| SUH DAEWOONG | 3 | 2012–2013 |
| XU DINGYING | 3 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Gilbert, AZ, US | 27 | 2009–2020 |
| Chandler, AZ, US | 14 | 2008–2015 |
| Saratoga, California, US | 3 | 2019–2021 |
| AZ, US | 1 | 2010 |
| Troy, New York, US | 1 | 2004 |