LexDanaLexDanabeta
Inventor

Xiying Costa

Inventor
San Jose, CA, US

Overview

38→
Patents
2013–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 38 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores35%
H10BElectronic memory devices25%
H01LSemiconductor devices15%
H10DInorganic electric semiconductor devices10%
G06FElectric digital data processing6%
H10NElectric solid-state devices not otherwise provided for6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%
PatentTitleYear
10,573,388Non-volatile storage system with adjustable select gates as a function of temperature202010,388,390Word line dependent pass voltages in non-volatile memory201910,355,007Three-dimensional memory structure having a back gate electrode201910,283,208Word line dependent pass voltages in non-volatile memory201910,056,399Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same201810,049,758Word line dependent pass voltages in non-volatile memory20189,672,917'Stacked vertical memory array architectures, systems and methods'20179,515,080'Vertical NAND and method of making thereof using sequential stack etching and landing pad'20169,460,799'Recovery of partially programmed block in non-volatile memory'20169,331,090'Compact three dimensional vertical NAND and method of making thereof'20169,330,778'Group word line erase and erase-verify methods for 3D non-volatile memory'20169,240,241'Pseudo block operation mode in 3D NAND'20169,177,673'Selection of data for redundancy calculation by likely error rate'20159,142,304'Erase operation for 3D non-volatile memory with controllable gate-induced drain leakage current'20159,136,022'Selection of data for redundancy calculation by likely error rate'20159,099,202'3D stacked non-volatile storage programming to conductive state'20159,047,973'Group word line erase and erase-verify methods for 3D non-volatile memory'20159,019,775'Erase operation for 3D non-volatile memory with controllable gate-induced drain leakage current'20158,934,292'Balanced method for programming multi-layer cell memories'20158,923,054'Pseudo block operation mode in 3D NAND'20148,913,431'Pseudo block operation mode in 3D NAND'20148,908,435'Erase operation with controlled select gate voltage for 3D non-volatile memory'20148,908,444'Erase for 3D non-volatile memory with sequential selection of word lines'20148,885,412'Erase operation with controlled select gate voltage for 3D non-volatile memory'20148,884,357'Vertical NAND and method of making thereof using sequential stack etching and landing pad'20148,883,589'Counter doping compensation methods to improve diode performance'20148,878,278'Compact three dimensional vertical NAND and method of making thereof'20148,879,333'Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits'20148,867,271'Threshold voltage adjustment for a select gate transistor in a stacked non-volatile memory device'20148,861,280'Erase for 3D non-volatile memory with sequential selection of word lines'20148,848,430'Step soft program for reversible resistivity-switching elements'20148,824,211'Group word line erase and erase-verify methods for 3D non-volatile memory'20148,787,094'Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits'20148,737,111'Memory cell with resistance-switching layers'20148,649,219'Erase inhibit for 3D non-volatile memory'20148,551,855'Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same'20138,488,382'Erase inhibit for 3D non-volatile memory'20138,481,396'Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same'2013

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2013–2016Patents assigned to SANDISK TECHNOLOGIES INC (25)· patent assignee history
2013–2015Patents assigned to COSTA XIYING (10)· patent assignee history
2013–2015Patents assigned to SANDISK 3D LLC (6)· patent assignee history
2013–2015Patents assigned to LI HAIBO (5)· patent assignee history
2013–2020Based in San Jose, CA, US· patent location history
2015Based in Milpitas, CA, US· patent location history
2016–2019Patents assigned to SANDISK TECHNOLOGIES LLC (8)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SANDISK TECHNOLOGIES INC252013–2016
COSTA XIYINGself102013–2015
SANDISK TECHNOLOGIES LLC82016–2019
SANDISK 3D LLC62013–2015
LI HAIBO52013–2015
Locations
LocationPatentsSpan
San Jose, California, US362013–2020
Milpitas, California, US22015