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Inventor

Shyue-Shyh Lin

Inventor
Zhubei City, TW

Overview

27→
Patents
1997–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 27 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices34%
H01LSemiconductor devices22%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
G06FElectric digital data processing3%
C23CCoating metallic material2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
G11CStatic stores2%
H10BElectronic memory devices2%
PatentTitleYear
10,535,655Integrated circuits and manufacturing methods thereof202010,515,856Method of making a FinFET, and FinFET formed by the method201910,224,245Method of making a finFET, and finFET formed by the method20199,553,043'Interconnect structure having smaller transition layer via'20179,543,193'Non-hierarchical metal layers for integrated circuits'20179,385,213'Integrated circuits and manufacturing methods thereof'20169,312,179'Method of making a finFET, and finFET formed by the method'20169,312,260'Integrated circuits and manufacturing methods thereof'20169,117,882'Non-hierarchical metal layers for integrated circuits'20159,111,768'Semiconductor devices, methods of manufacture thereof, and methods of forming resistors'20159,070,624'Semiconductor device including polysilicon resistor and metal gate resistor and methods of fabricating thereof'20158,994,116'Hybrid gate process for fabricating FinFET device'20158,859,386'Semiconductor devices, methods of manufacture thereof, and methods of forming resistors'20148,796,095'Integrated method for forming metal gate FinFET devices'20148,609,495'Hybrid gate process for fabricating finfet device'20138,507,957'Integrated circuit layouts with power rails under bottom metal layer'20138,473,888'Systems and methods of designing integrated circuits'20138,431,985'Layout and process of forming contact plugs'20138,373,219'Method of fabricating a gate stack integration of complementary MOS device'20138,362,573'Integrated circuits and manufacturing methods thereof'20138,356,262'Cell architecture and method'20138,173,499'Method of fabricating a gate stack integration of complementary MOS device'20128,034,677'Integrated method for forming high-k metal gate FinFET devices'20117,663,237'Butted contact structure'20107,349,234'Magnetic memory array'20086,825,133'Use of fluorine implantation to form a charge balanced nitrided gate dielectric layer'20045,614,270'Method of improving electrical characteristics of a liquid phase deposited silicon dioxide film by plasma treatment'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2016Based in Hsinchu, TW· patent location history
2004–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (20)· patent assignee history
2004Based in Chu-Nan, Miao-Li Hsien, TW· patent location history
2012–2017Patents assigned to LIN SHYUE-SHYH (15)· patent assignee history
2013–2016Patents assigned to TIEN LI-CHUN (6)· patent assignee history
2013–2017Patents assigned to LU LEE-CHUNG (5)· patent assignee history
2013–2019Based in Zhubei City, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (6)· patent assignee history
2016Based in Chutung, TW· patent location history
2020Based in Hsinchu County, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG202004–2016
LIN SHYUE-SHYHself152012–2017
TAIWAN SEMICONDUCTOR MFG CO LTD62016–2020
TIEN LI-CHUN62013–2016
LU LEE-CHUNG52013–2017
Locations
LocationPatentsSpan
Zhubei City, TW132013–2019
Hsinchu, TW111997–2016
Hsinchu County, TW12020
Chutung, TW12016
Chu-Nan, Miao-Li Hsien, TW12004