Inventor
Huahung Kao
Inventor
San Jose, CA, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1058%
H01LSemiconductor devices24%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H05KPrinted circuits2%
H10DInorganic electric semiconductor devices2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
10,128,171Leadframe with improved half-etch layout to reduce defects caused during singulation20189,666,571'Package-on-package structures'20179,543,236'Pad configurations for an electronic package assembly'20179,524,927'Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types'20169,355,951'Interconnect layouts for electronic assemblies'20169,331,052'Pad configurations for an electronic package assembly'20169,209,163'Package-on-package structures'20159,123,699'Formation of package pins in semiconductor packaging'20158,963,342'Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types'20158,940,585'Single layer BGA substrate process'20158,912,664'Leadless multi-chip module structure'20148,860,193'Pad configurations for an electronic package assembly'20148,686,547'Stack die structure for stress reduction and facilitation of electromagnetic shielding'20148,673,689'Single layer BGA substrate process'20148,669,139'Leadless multi-chip module structure'20148,455,347'Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types'20138,405,220'Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types'20138,358,013'Leadless multi-chip module structure'20138,319,353'Pre-formed conductive bumps on bonding pads'20128,030,098'Pre-formed conductive bumps on bonding pads'20117,999,395'Pillar structure on bump pad'20117,956,474'Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types'20117,825,521'Stack die packages'20107,586,199'Structures, architectures, systems, methods, algorithms and software for configuring and integrated circuit for multiple packaging types'20097,560,309'Drop-in heat sink and exposed die-back for molded flip die package'20097,535,110'Stack die packages'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2018Patents assigned to MARVELL INT LTD (16)· patent assignee history
2009–2017Patents assigned to MARVELL WORLD TRADE LTD (10)· patent assignee history
2009–2018Based in San Jose, CA, US· patent location history
2012–2016Patents assigned to KAO HUAHUNG (10)· patent assignee history
2012–2016Patents assigned to LIOU SHIANN-MING (8)· patent assignee history
2013Patents assigned to LEISTIKO TYSON (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MARVELL INT LTD | 16 | 2009–2018 |
| KAO HUAHUNGself | 10 | 2012–2016 |
| MARVELL WORLD TRADE LTD | 10 | 2009–2017 |
| LIOU SHIANN-MING | 8 | 2012–2016 |
| LEISTIKO TYSON | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 26 | 2009–2018 |