Inventor
Valentina Salapura
Inventor
Chappaqua, NY, US
Overview
Patents· 500 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing60%
H04LTransmission of digital information, e.g. telegraphic communication8%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
G06NComputing arrangements based on specific computational models3%
G06KGraphical data reading2%
G06TImage data processing or generation, in general1%
G06VImage or video recognition or understanding1%
G10LSpeech analysis techniques or speech synthesis1%
G09BEducational or demonstration appliances1%
PatentTitleYear
11,120,352Cognitive monitoring202111,119,785Delaying branch prediction updates specified by a suspend branch prediction instruction until after a transaction is completed202111,106,490Context switch by changing memory pointers202111,099,782Portions of configuration state registers in-memory202111,093,145Protecting in-memory configuration state registers202111,087,264Crowdsourcing of meetings202111,061,576Read-only table of contents register202111,061,575Read-only table of contents register202111,050,637Resource lifecycle optimization in disaggregated data centers202111,048,735Operation of a computer based on optimal problem solutions202111,049,613Security scanning for passengers with medical devices202111,036,599Disaster recovery and replication according to workload priorities in disaggregated datacenters202111,030,049Data backup management during workload migration202111,017,103Securely transferring computation in a disaggregated environment using a processor group key202111,012,423Maximizing resource utilization through efficient component communication in disaggregated datacenters202111,010,164Predicting a table of contents pointer value responsive to branching to a subroutine202110,990,888Cognitive monitoring202110,983,881Disaster recovery and replication in disaggregated datacenters202110,977,085Optimizing dynamical resource allocations in disaggregated data centers202110,976,931Automatic pinning of units of memory202110,977,185Initializing a data structure for use in predicting table of contents pointer values202110,977,957Music practice feedback202110,970,061Rolling upgrades in disaggregated systems202110,963,261Sharing snapshots across save requests202110,963,382Table of contents cache entry having a pointer for a range of addresses202110,958,610Generating alerts based on predicted mood responses to received electronic messages202110,956,831Detecting interaction during meetings202110,949,350Table of contents cache entry having a pointer for a range of addresses202110,936,374Optimizing dynamic resource allocations for memory-dependent workloads in disaggregated data centers202110,936,314Suppressing branch prediction on a repeated execution of an aborted transaction202110,929,135Predicting and storing a predicted target address in a plurality of selected locations202110,929,297Prefetch protocol for transactional memory202110,915,493Component building blocks and optimized compositions thereof in disaggregated datacenters202110,915,439Prefetch insensitive transactional memory202110,915,373Enabling rewire-aware MapReduce cluster in disaggregated systems202110,915,370Inter-host communication without data copy in disaggregated systems202110,908,911Predicting and storing a predicted target address in a plurality of selected locations202110,901,741Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence202110,901,738Bulk store and load operations of configuration state registers202110,901,918Constructing flexibly-secure systems in a disaggregated environment202110,896,030Code generation relating to providing table of contents pointer values202110,891,206Disaster recovery orchestration and capacity planning in disaggregated datacenters202110,891,133Code-specific affiliated register prediction202110,893,096Optimizing dynamical resource allocations using a data heat map in disaggregated data centers202110,884,821Measuring utilization of resources in datacenters202110,884,930Set table of contents (TOC) register instruction202110,885,166Computer security protection via dynamic computer system certification202110,884,929Set table of contents (TOC) register instruction202110,884,931Interprocessor memory status communication202110,884,746Determining and predicting affiliated registers based on dynamic runtime control flow analysis202110,884,748Providing a predicted target address to multiple locations based on detecting an affiliated relationship202110,885,556Fashion display system, method, recording medium and display apparatus202110,884,747Prediction of an affiliated register202110,884,745Providing a predicted target address to multiple locations based on detecting an affiliated relationship202110,876,228Enabling end of transaction detection using speculative look ahead202010,853,249Read and write sets for transactions of a multithreaded computing environment202010,841,367Optimizing dynamical resource allocations for cache-dependent workloads in disaggregated data centers202010,838,866Set table of contents (TOC) register instruction202010,838,482SLA-based power management in disaggregated computing systems202010,838,733Register context restoration based on rename register recovery202010,838,803Resource provisioning and replacement according to a resource failure analysis in disaggregated data centers202010,831,698Maximizing high link bandwidth utilization through efficient component communication in disaggregated datacenters202010,831,457Code generation relating to providing table of contents pointer values202010,831,580Diagnostic health checking and replacement of resources in disaggregated data centers202010,819,599Energy consumption as a measure of utilization and work characterization in a system202010,802,988Dynamic memory-based communication in disaggregated datacenters202010,789,576Meeting management system202010,768,931Fine-grained management of exception enablement of floating point controls202010,768,961Virtual machine seed image replication through parallel deployment202010,761,751Configuration state registers grouped based on functional affinity202010,761,983Memory based configuration state registers202010,761,915Preemptive deep diagnostics and health checking of resources in disaggregated data centers202010,754,656Determining and predicting derived values202010,754,720Health check diagnostics of resources by instantiating workloads in disaggregated data centers202010,754,738Using transactional execution for reliability and recovery of transient failures202010,747,628Using transactional execution for reliability and recovery of transient failures202010,740,106Determining if transactions that are about to run out of resources can be salvaged or need to be aborted202010,740,067Selective updating of floating point controls202010,740,097Embedding global barrier and collective in a torus network202010,733,091Read and write sets for ranges of instructions of transactions202010,732,930Compiler controls for program language constructs202010,725,918Table of contents cache entry having a pointer for a range of addresses202010,725,739Compiler controls for program language constructs202010,725,900Read and write sets for ranges of instructions of transactions202010,719,322Techniques for facilitating cracking and fusion within a same instruction group202010,719,328Determining and predicting derived values used in register-indirect branching202010,719,418Replicating workload data according to a degree of resiliency for disaster recovery in disaggregated datacenters202010,713,051Replacing table of contents (TOC)-setting instructions in code with TOC predicting instructions202010,713,050Replacing Table of Contents (TOC)-setting instructions in code with TOC predicting instructions202010,705,973Initializing a data structure for use in predicting table of contents pointer values202010,698,686Configurable architectural placement control202010,701,141Managing software licenses in a disaggregated environment202010,694,373Privacy protection of images in online settings202010,691,600Table of contents cache entry having a pointer for a range of addresses202010,684,852Employing prefixes to control floating point operations202010,684,853Employing prefixes to control floating point operations202010,671,386Compiler controls for program regions202010,671,557Dynamic component communication using general purpose links between respectively pooled together of like typed devices in disaggregated datacenters202010,671,393Techniques for facilitating cracking and fusion within a same instruction group202010,664,181Protecting in-memory configuration state registers202010,656,946Predicting a table of contents pointer value responsive to branching to a subroutine202010,649,785Tracking changes to memory via check and recovery202010,642,700System, method and recording medium for antifragile computing problem management202010,642,757Single call to perform pin and unpin operations202010,635,441Caller protected stack return address in a hardware managed stack architecture202010,637,733Dynamic grouping and repurposing of general purpose links in disaggregated datacenters202010,635,475Migration-adjusted problem ticket analysis and consolidation202010,635,602Address translation prior to receiving a storage reference using the address to be translated202010,620,955Predicting a table of contents pointer value responsive to branching to a subroutine202010,614,428Recipe selection system with bidirectional calendar interface202010,599,615System, method, and recording medium for recycle bin management based on cognitive factors202010,601,725SLA-based agile resource provisioning in disaggregated computing systems202010,600,326Method for guiding an emergency vehicle using an unmanned aerial vehicle202010,601,903Optimizing dynamical resource allocations based on locality of resources in disaggregated data centers202010,599,148Mobile audio input device controller202010,592,164Portions of configuration state registers in-memory202010,594,810Enhancing natural language processing query/answer systems using social network analysis202010,594,811Enhancing natural language processing query/answer systems using social network analysis202010,592,249Selective suppression of instruction translation lookaside buffer (ITLB) access202010,592,251Register restoration using transactional memory register snapshots202010,585,697Dynamic prediction of hardware transaction resource requirements202010,585,808Single call to perform pin and unpin operations202010,580,144Method and system for tracking holographic object202010,579,385Prediction of an affiliated register202010,572,298Dynamic prediction of hardware transaction resource requirements202010,565,117Instruction to cancel outstanding cache prefetches202010,564,974Determining and predicting affiliated registers based on dynamic runtime control flow analysis202010,565,003Hint instruction for managing transactional aborts in transactional memory computing environments202010,558,560Prefetch insensitive transactional memory202010,558,366Automatic pinning of units of memory202010,558,461Determining and predicting derived values used in register-indirect branching202010,553,045Cognitive testing, debugging, and remediation of drone202010,552,164Sharing snapshots between restoration and recovery202010,552,070Separation of memory-based configuration state registers based on groups202010,545,766Register restoration using transactional memory register snapshots202010,545,560Power management and utilization detection of computing components202010,540,184Coalescing store instructions for restoration202010,534,609Code-specific affiliated register prediction202010,534,598Rolling upgrades in disaggregated systems202010,534,713Deferred response to a prefetch request202010,529,249Music practice feedback system, method, and recording medium202010,521,262Memory access request for a memory protocol201910,514,913Compiler controls for program regions201910,503,538Delaying branch prediction updates specified by a suspend branch prediction instruction until after a transaction is completed201910,503,401Opportunistic data analytics using memory bandwidth in disaggregated computing systems201910,496,437Context switch by changing memory pointers201910,489,382Register restoration invalidation based on a context switch201910,484,300Admission control based on the end-to-end availability201910,481,909Predicted null updates201910,481,908Predicted null updated201910,474,577Prefetch protocol for transactional memory201910,474,576Prefetch protocol for transactional memory201910,453,172Sparse-data generative model for pseudo-puppet memory recast201910,441,892Pseudo-sentient doll override system, method, and recording medium for pseudo-sentient doll override201910,438,123Cognitive publication subscriber system, method, and recording medium with a firewall201910,409,509Multi-tenant memory service for memory pool architectures201910,401,940Power management in disaggregated computing systems201910,395,425System, method and recording medium for mannequin pose control201910,387,209Dynamic transparent provisioning of resources for application specific resources201910,379,851Fine-grained management of exception enablement of floating point controls201910,372,611Deferred response to a prefetch request201910,365,927Non-default instruction handling within transaction201910,360,077Measuring utilization of resources in datacenters201910,353,734Prioritization of transactions based on execution by transactional core with super core indicator201910,346,197Inducing transactional aborts in other processing threads201910,346,169Selective suppression of instruction cache-related directory access201910,346,305Interprocessor memory status communication201910,331,565Transactional memory system including cache versioning architecture to implement nested transactions201910,324,715Compiler controls for program regions201910,318,240Read and set floating point control register instruction201910,310,855Non-default instruction handling within transaction201910,310,952Using transactional execution for reliability and recovery of transient failures201910,310,814Read and set floating point control register instruction201910,293,534Hybrid tracking of transaction read and write sets201910,289,499Using transactional execution for reliability and recovery of transient failures201910,289,414Suppressing branch prediction on a repeated execution of an aborted transaction201910,289,979Greeting agent for meeting introductions201910,270,775Mechanism for creating friendly transactions with credentials201910,270,773Mechanism for creating friendly transactions with credentials201910,261,826Suppressing branch prediction updates upon repeated execution of an aborted transaction until forward progress is made201910,262,302Recipe selection system with bidirectional calendar interface201910,255,136Data backup management during workload migration201910,255,189Mechanism for creating friendly transactions with credentials201910,243,936Automatic security parameter management and renewal201910,244,013Managing drop-ins on focal points of activities201910,235,297Mechanism for creating friendly transactions with credentials201910,235,172Branch predictor performing distinct non-transaction branch prediction functions and transaction branch prediction functions201910,228,943Prefetching of discontiguous storage locations in anticipation of transactional execution201910,223,268Transactional memory system including cache versioning architecture to implement nested transactions201910,223,154Hint instruction for managing transactional aborts in transactional memory computing environments201910,216,635Instruction to cancel outstanding cache prefetches201910,210,019Hint instruction for managing transactional aborts in transactional memory computing environments201910,185,677Non-interfering transactions201910,180,921Non-interfering transactions201910,178,741Proactive image obfuscation201910,169,716Interactive learning201910,171,375Constructing computing systems with flexible capacity of resources using disaggregated systems201910,168,961Hardware transaction transient conflict resolution201910,169,710Automated decision support provenance and simulation201910,162,744Prefetch insensitive transactional memory201810,162,743Prefetch insensitive transactional memory201810,152,418Speculation control for improving transaction success rate, and instruction therefor201810,152,419Deferred response to a prefetch request201810,146,692Deferred response to a prefetch request201810,133,954Visual comparisons using personal objects201810,129,169Specifying a highly-resilient system in a disaggregated compute environment201810,120,802Transactional memory coherence control201810,120,804Hybrid tracking of transaction read and write sets201810,120,745Providing instructions to protect stack return addresses in a hardware managed stack architecture201810,120,803Transactional memory coherence control201810,114,890Goal based conversational serendipity inclusion201810,095,918System and method for interpreting interpersonal communication201810,083,076Salvaging lock elision transactions with instructions to change execution type201810,076,632Sensory feedback system with active learning201810,078,515Tracking operand liveness information in a computer system and performing function based on the liveness information201810,066,391Floor covering having adjustable hardness201810,061,588Tracking operand liveness information in a computer system and performing function based on the liveness information201810,061,705Identifying instructions for decode-time instruction optimization grouping in view of cache boundaries201810,063,493Application-based elastic resource provisioning in disaggregated computing systems201810,061,703Prefetch insensitive transactional memory201810,061,586Latent modification instruction for transactional execution201810,055,230Accurate tracking of transactional read and write sets with speculation201810,042,749Prefetch insensitive transactional memory201810,042,761Read and write sets for transactions of a multithreaded computing environment201810,042,765Read and write sets for transactions of a multithreaded computing environment201810,002,533System, method and recording medium for emergency vehicle route guidance20189,997,050Tracking a user based on an electronic noise profile20189,983,904Multithreaded transactions20189,971,713Multi-petascale highly efficient parallel supercomputer20189,971,628Salvaging hardware transactions20189,971,635Method and apparatus for a hierarchical synchronization barrier in a multi-node system20189,971,626Coherence protocol augmentation to indicate transaction status20189,952,804Hardware transaction transient conflict resolution20189,952,943Salvaging hardware transactions20189,952,976Allowing non-cacheable loads within a transaction20189,946,494Hardware transaction transient conflict resolution20189,940,135Instruction stream modification for memory transaction protection20189,940,538Visual comparisons using personal objects20189,940,242Techniques for identifying instructions for decode-time instruction optimization grouping in view of cache boundaries20189,934,095System, method and recording medium for antifragile computing problem management20189,934,363Automatically assessing the mental state of a user via drawing pattern detection and machine learning20189,928,064'Instruction stream modification for memory transaction protection'20189,921,834'Prefetching of discontiguous storage locations in anticipation of transactional execution'20189,921,843'Predictive fetching and decoding for selected instructions'20189,921,872'Interprocessor memory status communication'20189,923,938'Managing drop-ins on focal points of activities'20189,916,180'Interprocessor memory status communication'20189,916,636'Dynamically provisioning and scaling graphic processing units for data analytic workloads in a hardware cloud'20189,916,179'Interprocessor memory status communication'20189,912,646'Automatic security parameter management and renewal'20189,904,572'Dynamic prediction of hardware transaction resource requirements'20189,898,296'Selective suppression of instruction translation lookaside buffer (ITLB) access'20189,891,919'Caller protected stack return address in a hardware managed stack architecture'20189,891,959'Stage-aware performance modeling for computer cluster sizing'20189,892,052'Hybrid tracking of transaction read and write sets'20189,873,039Automatic trigger of integrated game actions for exercise and well being20189,870,253'Enabling end of transaction detection using speculative look ahead'20189,870,254'Multithreaded transactions'20189,870,210'Partition mobility for partitions with extended code'20189,858,189'Hybrid tracking of transaction read and write sets'20189,858,058'Partition mobility for partitions with extended code'20189,858,074'Non-default instruction handling within transaction'20189,851,974Selective suppression of instruction cache-related directory access20179,851,971Latent modification instruction for transactional execution20179,852,035High availability dynamic restart priority calculator20179,846,593Predicting the length of a transaction20179,842,510'Music practice feedback system, method, and recording medium'20179,836,695Automated decision support provenance and simulation20179,836,055Mobile audio input device controller20179,830,159Suspending branch prediction upon entering transactional execution mode20179,815,197'Device, system and method for tracking and replacing lights with automated vehicles'20179,817,693'Coherence protocol augmentation to indicate transaction status'20179,811,281'Multi-tenant memory service for memory pool architectures'20179,798,635'Service level agreement-based resource allocation for failure recovery'20179,792,148'Prioritization of transactions based on execution progress'20179,792,149'Prioritization of transactions based on execution progress'20179,772,874'Prioritization of transactions based on execution by transactional core with super core indicator'20179,772,786'Address probing for transaction'20179,766,829'Address probing for transaction'20179,760,495'Hybrid tracking of transaction read and write sets'20179,760,766'System and method for interpreting interpersonal communication'20179,760,397'Interprocessor memory status communication'20179,760,494'Hybrid tracking of transaction read and write sets'20179,753,764'Alerting hardware transactions that are about to run out of space'20179,740,616'Multi-granular cache management in multi-processor computing environments'20179,740,491'Instruction group formation techniques for decode-time instruction optimization based on feedback'20179,733,940'Techniques for instruction group formation for decode-time instruction optimization based on feedback'20179,736,446'Automated color adjustment of media files'20179,734,428'Visual comparisons using personal objects'20179,727,337'Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers'20179,727,370'Collecting memory operand access characteristics during transactional execution'20179,729,921'Television program optimization for user exercise'20179,727,336'Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers'20179,720,725'Prefetching of discontiguous storage locations as part of transactional execution'20179,720,662'Selectively controlling use of extended mode features'20179,720,837'Allowing non-cacheable loads within a transaction'20179,720,661'Selectively controlling use of extended mode features'20179,715,449'Hierarchical translation structures providing separate translations for instruction fetches and data accesses'20179,710,382'Hierarchical translation structures providing separate translations for instruction fetches and data accesses'20179,710,271'Collecting transactional execution characteristics during transactional execution'2017Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2021Patents assigned to IBM (488)· patent assignee history
2004–2005Based in Yorktown, NY, US· patent location history
2005–2021Based in Chappaqua, NY, US· patent location history
2006–2021Based in Yorktown Heights, NY, US· patent location history
2011–2018Patents assigned to SALAPURA VALENTINA (58)· patent assignee history
2011–2015Patents assigned to CHEN DONG (9)· patent assignee history
2012–2018Patents assigned to GSCHWIND MICHAEL K (22)· patent assignee history
2012–2016Patents assigned to WISNIEWSKI ROBERT W (13)· patent assignee history
2014–2015Based in Mount Kisco, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 488 | 2004–2021 |
| SALAPURA VALENTINAself | 58 | 2011–2018 |
| GSCHWIND MICHAEL K | 22 | 2012–2018 |
| WISNIEWSKI ROBERT W | 13 | 2012–2016 |
| CHEN DONG | 9 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Chappaqua, New York, US | 472 | 2005–2021 |
| Yorktown Heights, New York, US | 23 | 2006–2021 |
| Mount Kisco, New York, US | 3 | 2014–2015 |
| Yorktown, New York, US | 2 | 2004–2005 |