Inventor
Nadine Collaert
Inventor
Blanden, BE
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices30%
H01LSemiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
B82YSpecific uses or applications of nanostructures7%
G01NInvestigating or analysing materials by determining their chemical or physical properties5%
B28DWorking stone or stone-like materials2%
G06NComputing arrangements based on specific computational models2%
G10LSpeech analysis techniques or speech synthesis2%
G11CStatic stores2%
PatentTitleYear
10,930,750Method for forming a qubit device202110,768,138Protecting a substrate region during fabrication of a FET sensor202010,367,031Sequential integration process201910,347,536Semi-sequential 3D integration201910,309,925FET biosensor201910,274,452Micro-stimulation and data acquisition from biological cells201910,236,183Monolithic integration of semiconductor materials201910,163,714Semi-sequential 3D integration20189,633,891'Method for forming a transistor structure comprising a fin-shaped channel structure'20179,601,488'Gate-all-around semiconductor device and method of fabricating the same'20179,419,110'Method for reducing contact resistance in MOS'20169,324,818'Gate-all-around semiconductor device and method of fabricating the same'20169,257,539'Method for manufacturing transistor and associated device'20168,445,963'Multi-gate semiconductor devices with improved carrier mobility'20138,391,059'Methods for operating a semiconductor device'20138,319,295'Use of F-based gate etch to passivate the high-k/metal gate stack for deep submicron transistor technologies'20127,842,559'Method of fabricating multi-gate semiconductor devices with improved carrier mobility'20107,494,902'Method of fabricating a strained multi-gate transistor'20096,974,729'Integrated semiconductor fin device and a method for manufacturing such device'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2009Patents assigned to IMEC INTER UNI MICRO ELECTR (2)· patent assignee history
2005–2021Based in Blanden, BE· patent location history
2010–2019Patents assigned to IMEC (5)· patent assignee history
2012–2013Patents assigned to COLLAERT NADINE (3)· patent assignee history
2012–2019Patents assigned to UNIV LEUVEN KATH (2)· patent assignee history
2016–2021Patents assigned to IMEC VZW (12)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IMEC VZW | 12 | 2016–2021 |
| IMEC | 5 | 2010–2019 |
| COLLAERT NADINEself | 3 | 2012–2013 |
| IMEC INTER UNI MICRO ELECTR | 2 | 2005–2009 |
| UNIV LEUVEN KATH | 2 | 2012–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Blanden, BE | 19 | 2005–2021 |