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Inventor

Chauchin Su

Inventor
Taipei, TW

Overview

4→
Patents
2007–2014
Patent span
Physics
Primary field (CPC G)

Patents· 4 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing40%
G01RMeasuring electric variables20%
H03KPulse technique20%
H04LTransmission of digital information, e.g. telegraphic communication20%
PatentTitleYear
8,806,414'Method and system for layout parasitic estimation'20148,726,207'On-the-fly device characterization from layouts of circuits'20147,764,086'Buffer circuit'20107,228,479'IEEE Std. 1149.4 compatible analog BIST methodology'2007

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2014Based in Taipei, TW· patent location history
2014Patents assigned to CHEN CHIEN-WEN (2)· patent assignee history
2014Patents assigned to HUANG MU-JEN (2)· patent assignee history
2014Patents assigned to JIANG YU-SIAN (2)· patent assignee history
2014Patents assigned to SU CHAUCHIN (2)· patent assignee history
2014Patents assigned to TAIWAN SEMICONDUCTOR MFG (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CHEN CHIEN-WEN22014
HUANG MU-JEN22014
JIANG YU-SIAN22014
SU CHAUCHINself22014
TAIWAN SEMICONDUCTOR MFG22014
Locations
LocationPatentsSpan
Taipei, TW42007–2014